Analog Devices Inc. LTC2913IDD-2#PBF
- Part No.:
- LTC2913IDD-2#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC2913IDD-2#PBF.pdf
- Description:
- IC SUPERVISOR 2 CHANNEL 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2913IDD-2#PBF from Analog Devices (formerly Linear Technology) is a dual-input, dual-threshold voltage monitor IC designed for simultaneous undervoltage (UV) and overvoltage (OV) supervision of two independent power rails. It features adjustable UV/OV trip points with ±1.5% threshold accuracy, 44 μA quiescent current, open-drain UV/OV outputs, and a dedicated DIS pin to disable both outputs-enabling clean system reset control in desktop computers and network servers.
For engineers reviewing the LTC2913IDD-2#PBF datasheet, LTC2913IDD-2#PBF pinout, LTC2913IDD-2#PBF application, or LTC2913IDD-2#PBF equivalent, key selection considerations include its 10-lead DFN (3mm × 3mm) package, guaranteed operation down to VCC = 1 V, adjustable reset timeout via external capacitor, glitch-immune comparator architecture, and explicit DIS input functionality distinguishing it from the latch-enabled LTC2913-1 variant.
Technical Context
The LTC2913IDD-2#PBF implements two independent voltage monitoring channels (VH1/VL1 and VH2/VL2), each comparing input voltages against a common 500 mV internal reference. Its DIS pin (Pin 8) provides active-high output disable-forcing UV and OV high regardless of input faults except during VCC undervoltage lockout (UVLO). The TMR pin (Pin 9) accepts an external capacitor to set a programmable timeout period (6–14 ms typical at 1 nF) that holds outputs asserted after fault clearance.
Unlike the LTC2913-1, this variant lacks latch capability and replaces the LATCH pin with DIS. Its internal shunt regulator enables direct connection to supplies up to 6 V or regulated operation from higher voltages using an external series resistor. Input glitch rejection is achieved via integrated low-pass filtering on each comparator output, eliminating need for external hysteresis while maintaining ±1.5% threshold accuracy across –40°C to 85°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1 V to 6 V - supports brownout detection and valid operation even during deep supply sag |
| Threshold Accuracy | ±1.5% - ensures precise UV/OV trip points across full temperature range without calibration |
| Quiescent Current | 44 μA typical - enables micropower system monitoring without impacting standby efficiency |
| UV/OV Timeout | 6–14 ms (at CTMR = 1 nF) - guarantees minimum reset pulse width for reliable processor initialization |
| Input Voltage Range | VHn/VLn: –0.3 V to 7.5 V - accommodates wide-rail monitoring including negative biasing schemes |
| Output Type | Open-drain UV/OV - allows wired-OR reset bus sharing and flexible pull-up voltage selection |
| DIS Input Threshold | VIL = 0.8 V, VIH = 1.2 V - compatible with standard CMOS logic and robust against noise |
Pinout & Package
Package: 10-lead (3mm × 3mm) plastic DFN with exposed pad (Pin 11, optional GND connection).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VH1 (Pin 1) | Channel 1 High-Side Monitor Input | Detects undervoltage when voltage falls below 500 mV; tie to VCC if unused |
| VL1 (Pin 2) | Channel 1 Low-Side Monitor Input | Detects overvoltage when voltage rises above 500 mV; tie to GND if unused |
| VH2 (Pin 3) | Channel 2 High-Side Monitor Input | Independent second UV path; identical electrical behavior to VH1 |
| VL2 (Pin 4) | Channel 2 Low-Side Monitor Input | Independent second OV path; identical electrical behavior to VL1 |
| GND (Pin 5) | Device Ground Reference | Return path for all internal circuitry and external timing capacitor |
| OV (Pin 6) | Overvoltage Output | Open-drain logic-low assertion during OV condition; disabled when DIS = high |
| UV (Pin 7) | Undervoltage Output | Open-drain logic-low assertion during UV condition; disabled when DIS = high |
| DIS (Pin 8) | Output Disable Control | Active-high input disabling both UV and OV outputs except during VCC UVLO |
| TMR (Pin 9) | Reset Timeout Timing Node | Connects to external capacitor to set UV/OV assertion hold time; tie to VCC to bypass |
| VCC (Pin 10) | Supply Input / Shunt Regulator | Operates as direct supply (≤6 V) or shunt-regulated input (>6 V) with internal 6.6 V clamp |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent UV/OV monitoring | Simultaneously supervises two power rails with separate VH/VL inputs per channel |
| Output disable via DIS pin | Enables deterministic reset state control during boot, debug, or safe mode entry |
| Glitch-immune comparator architecture | Eliminates false triggering from transient noise without adding threshold hysteresis error |
| Adjustable reset timeout | Programmable 6–14 ms minimum pulse width via single external capacitor on TMR pin |
| Micropower operation | 44 μA supply current allows continuous monitoring in battery-backed or ultra-low-power systems |
Applications
| Desktop Power Sequencing | Network Server Core Rail Monitoring |
|---|---|
Use Scenario: Supervising 12 V and 5 V input rails in ATX-compatible desktop motherboards during cold start and thermal throttling events. IC Role / Device Role / Timing Role: LTC2913IDD-2#PBF acts as primary UV/OV detector, asserting coordinated reset signals only after both rails stabilize within tolerance. Use Value: Prevents CPU lockup by ensuring stable core I/O voltages before release of processor reset, leveraging ±1.5% threshold accuracy and 44 μA quiescent draw. | Use Scenario: Monitoring redundant 3.3 V and 5 V power modules in blade server backplanes where rail failure must trigger immediate failover. IC Role / Device Role / Timing Role: LTC2913IDD-2#PBF serves as fault-detection interface between power modules and baseboard management controller (BMC), with DIS pin used to mask resets during hot-swap transitions. Use Value: Enables selective reset suppression via DIS input, avoiding unintended BMC reboots during live power module replacement. |
| Industrial PLC I/O Module Supply Check | Embedded Computing Board Brownout Protection |
Use Scenario: Verifying 24 V field power and 5 V logic rail integrity in programmable logic controller (PLC) digital I/O modules operating in electrically noisy factory environments. IC Role / Device Role / Timing Role: LTC2913IDD-2#PBF functions as noise-hardened supervisor, using internal low-pass filtering to reject EMI-induced transients on monitored rails. Use Value: Achieves reliable fault detection without external RC filters, reducing BOM count while maintaining ±1.5% trip accuracy across –40°C to 85°C industrial temperature range. | Use Scenario: Protecting ARM-based embedded computing boards from data corruption during AC adapter disconnection or battery depletion. IC Role / Device Role / Timing Role: LTC2913IDD-2#PBF monitors main 5 V and auxiliary 3.3 V rails, asserting UV only after sustained drop below threshold-preventing spurious resets from brief dips. Use Value: Guarantees minimum 6 ms reset pulse width (configurable up to 14 ms) to ensure complete SoC shutdown before power collapse. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual UV/OV monitoring applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC2913CMS-2 | Same functional spec, but in 10-lead MSOP package (4.9 mm × 3.0 mm) vs DFN (3.0 mm × 3.0 mm) | Preferred for through-hole prototyping or legacy PCB layouts with MSOP footprints | Select LTC2913CMS-2 when board space permits larger package or reflow compatibility with existing MSOP tooling is required |
| LTC2914HDD-1 | Quad-input UV/OV monitor with latch capability, 16-lead DFN, –40°C to 125°C rating | Suitable for automotive or extended-temperature applications requiring four rail supervision | Choose LTC2914HDD-1 only when monitoring >2 rails or needing automotive-grade temp range; not drop-in compatible |
Compared with LTC2913CMS-2, the LTC2913IDD-2#PBF offers identical electrical performance in a smaller 3mm × 3mm DFN footprint ideal for space-constrained designs; compared with LTC2914HDD-1, it provides simpler dual-rail supervision without latch complexity or over-specification for cost-sensitive industrial applications.
Availability
LTC2913IDD-2#PBF is available at Aetrix Electronics and suitable for desktop computers, network servers, and industrial PLCs requiring stable component supply with guaranteed long-term availability and traceable sourcing.
Supply support for LTC2913IDD-2#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its precision analog and power management product lines with full datasheet, simulation model, and application support.
The LTC2913 family is designed for high-accuracy, low-power voltage supervision in computing and communications infrastructure-emphasizing threshold stability, noise immunity, and compact packaging for multi-rail systems.
FAQ
What is the function of the DIS pin on the LTC2913IDD-2#PBF?
The DIS (Disable) pin on the LTC2913IDD-2#PBF is an active-high control input that forces both UV and OV outputs into a high-impedance (weakly pulled high) state, overriding all fault conditions except VCC undervoltage lockout (UVLO). When DIS is pulled high, the LTC2913IDD-2#PBF ceases asserting reset signals even if VH or VL inputs violate thresholds-enabling controlled reset suppression during system initialization or maintenance. Internal 2 μA pull-down ensures default operation when DIS is left unconnected.
Does the LTC2913IDD-2#PBF support operation below 2.3 V VCC?
Yes, the LTC2913IDD-2#PBF guarantees functional operation down to VCC = 1 V, including valid UV and OV output assertion and accurate threshold detection. At VCC = 1 V, the device maintains ±1.5% threshold accuracy and delivers VOL ≤ 0.15 V on UV/OV pins at 100 μA sink current. This enables brownout detection in deeply scaled systems where supply rails dip below conventional 2.3 V minimums-critical for reliable low-voltage sequencing in modern processors and FPGAs.
How is the reset timeout period set on the LTC2913IDD-2#PBF?
The reset timeout period on the LTC2913IDD-2#PBF is set by connecting an external capacitor (CTMR) between the TMR pin (Pin 9) and GND. The timeout tUOTO ≈ 9 ms/nF, yielding 8.5 ms typical at 1 nF. Capacitor values from 10 pF to >100 nF are supported, with leakage current <1.3 μA required for long timeouts. Tying TMR directly to VCC disables the timeout function entirely, causing UV/OV to deassert immediately upon fault clearance-providing flexibility for applications needing instantaneous reset release.
Can the LTC2913IDD-2#PBF monitor negative voltages?
No, the LTC2913IDD-2#PBF is specified only for positive voltage monitoring: VHn and VLn inputs accept 0 V to 7.5 V, with trip detection centered at +500 mV. It cannot directly supervise negative rails like –12 V or –5 V. For negative voltage monitoring, Analog Devices offers the LTC2909 (dual UV/OV plus negative rail support) or LTC2914 (quad UV/OV with up to two negative inputs), both requiring separate VCC biasing and different pin configurations-not functionally interchangeable with the LTC2913IDD-2#PBF.
What is the maximum input voltage allowed on VH1/VL1 pins of the LTC2913IDD-2#PBF?
The absolute maximum voltage on VH1, VL1, VH2, and VL2 pins of the LTC2913IDD-2#PBF is +7.5 V, with a lower limit of –0.3 V. This rating applies regardless of VCC level. Exceeding +7.5 V risks permanent damage due to internal ESD protection diode conduction. For monitoring rails above 7.5 V (e.g., 12 V), a resistive divider must be used to scale the input down to ≤7.5 V while preserving the 500 mV threshold relationship-ensuring the LTC2913IDD-2#PBF maintains ±1.5% accuracy across temperature and supply variations.
LTC2913IDD-2#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 2
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
LTC2913IDD-2#PBF FAQ
1.How can I place an order for LTC2913IDD-2#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2913IDD-2#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2913IDD-2#PBF reliable?
The price and inventory of LTC2913IDD-2#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2913IDD-2#PBF is usually 5 days.
3.What payment methods are accepted for LTC2913IDD-2#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2913IDD-2#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2913IDD-2#PBF?
LTC2913IDD-2#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2913IDD-2#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2913IDD-2#PBF?
For technical support, including LTC2913IDD-2#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2913IDD-2#PBF requirements.
6.How does Aetrix verify that LTC2913IDD-2#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2913IDD-2#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2913IDD-2#PBF meets industry standards.
7.What is the process for return or replacement of LTC2913IDD-2#PBF?
All LTC2913IDD-2#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2913IDD-2#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2913IDD-2#PBF part is unused and in its original packaging.
Return procedure for LTC2913IDD-2#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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