Analog Devices Inc. LTC2914IDHC-1#PBF
- Part No.:
- LTC2914IDHC-1#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 16-WFDFN Exposed Pad
- Datasheet:
-
LTC2914IDHC-1#PBF.pdf
- Description:
- IC SUPERVISOR 4 CHANNEL 16DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2914IDHC-1#PBF from Analog Devices (formerly Linear Technology) is a quad-input, latching overvoltage/undervoltage supervisor IC designed for simultaneous monitoring of four independent power rails in high-reliability systems. It delivers ±1.5% threshold accuracy over temperature, 62µA quiescent current, and supports both positive and negative voltage monitoring via programmable polarity selection. It is deployed in desktop/notebook computers and network servers for core/I/O rail supervision.
For engineers reviewing the LTC2914IDHC-1#PBF datasheet, LTC2914IDHC-1#PBF pinout, LTC2914IDHC-1#PBF application, or LTC2914IDHC-1#PBF equivalent, key selection considerations include its latching OV output (LTC2914-1 variant), adjustable reset timeout, buffered 1V reference, dual-polarity input capability, and guaranteed operation down to VCC = 1V.
Technical Context
The LTC2914IDHC-1#PBF implements four independent comparator pairs (VHn/VLn), each comparing input voltages against a precise 500mV internal threshold referenced to a buffered 1V reference. Its three-state SEL pin selects polarity configurations-positive, mixed, or negative-for inputs 3 and 4, enabling monitoring of up to two negative supplies without external components.
It features a dedicated TMR pin for setting an adjustable UV/OV timeout period (6–14ms with 1nF), a latching OV output cleared by the LATCH pin (active-low clear), and internal shunt regulation on VCC (6.6V typical) for operation from supplies >6V. Glitch filtering at each comparator input ensures noise immunity without added hysteresis error.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.3V to 6V direct supply; internal 6.6V shunt regulator enables use with higher-voltage sources via series resistor. |
| Threshold Accuracy | ±1.5% over –40°C to +85°C - ensures reliable trip points across industrial temperature range without calibration. |
| Quiescent Current | 62µA typical - enables always-on monitoring in battery-backed or low-power embedded systems. |
| Reference Output | 1.000V ±15mV buffered reference - drives ≤1mA load and enables accurate negative-rail monitoring with 3-resistor divider. |
| UV/OV Timeout | Adjustable 6–14ms (–40°C to +125°C) via external capacitor on TMR pin - guarantees minimum reset pulse width after fault clearance. |
| Input Voltage Range | VHn/VLn tolerate –0.3V to +7.5V - supports direct connection to negative rails when configured with SEL. |
| Output Type | Open-drain UV and OV outputs with weak internal pull-up to VCC - enables wired-OR reset bus and compatibility with 1V–6V logic levels. |
Pinout & Package
Package: 16-lead (5mm × 3mm) plastic DFN with exposed pad (Pin 17, optional GND connection). Operating temperature range: –40°C to +85°C (I-grade).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VH1–VH4 (Pins 1,3,5,7) | High-side voltage monitor inputs | Trigger undervoltage when below 0.5V (positive mode) or overvoltage when below 0.5V (negative mode, per SEL state). |
| VL1–VL4 (Pins 2,4,6,8) | Low-side voltage monitor inputs | Trigger overvoltage when above 0.5V (positive mode) or undervoltage when above 0.5V (negative mode, per SEL state). |
| VCC (Pin 16) | Supply input / shunt regulator | Accepts 2.3–6V directly; regulates >6V supplies internally (6.6V typical) - requires series resistor if source exceeds 6V. |
| TMR (Pin 15) | Reset timeout timing control | Connects to GND via capacitor (CTMR) to set 6–14ms timeout; tie to VCC to bypass timer entirely. |
| SEL (Pin 14) | Three-state polarity select | Connect to GND, VCC, or leave open to configure VH3/VL3 and VH4/VL4 as positive, mixed, or negative monitors. |
| LATCH (Pin 13) | OV latch clear/bypass | Pull low to latch OV output on fault; pull high to clear latch and enable standard timed OV behavior (LTC2914-1 function). |
| UV (Pin 12) | Common undervoltage output | Open-drain, active-low signal asserted when any monitored rail falls below threshold - held low for full timeout after recovery. |
| OV (Pin 11) | Common overvoltage output | Open-drain, active-low signal asserted when any monitored rail exceeds threshold - latched low until LATCH pin is pulled high. |
| REF (Pin 10) | Buffered 1V reference output | Stable, low-impedance 1.000V reference for negative-rail divider networks; sinks/sources ±1mA; stable with ≤1nF capacitive load. |
| GND (Pin 9) | Device ground reference | Primary return path for all analog and digital circuitry; exposed pad (Pin 17) may be connected here for improved thermal performance. |
Key Features
| Feature | Design Value |
|---|---|
| Latching OV output | Ensures persistent system reset during transient overvoltage events until explicitly cleared via LATCH pin - critical for fault containment in server PSUs. |
| Programmable dual-polarity monitoring | SEL pin configures two input pairs for negative-rail monitoring without external op-amps or level shifters - reduces BOM count and layout complexity. |
| Guaranteed operation at VCC ≥ 1V | Enables valid UV assertion and OV pull-up even during brown-out conditions - supports robust power sequencing in multi-rail systems. |
| Input glitch rejection | Integrated low-pass filtering at each comparator input eliminates false triggering from µs-scale noise without adding threshold hysteresis error. |
| Adjustable reset timeout | External capacitor on TMR pin sets precise 6–14ms delay - ensures sufficient settling time before releasing reset after rail stabilization. |
Applications
| Desktop & Notebook Computers | Network Servers |
|---|---|
|
Use Scenario: Monitoring 5V, 3.3V, 2.5V, and 1.8V core/I/O rails during boot and runtime. IC Role / Device Role / Timing Role: Quad UV/OV supervisor providing single-point reset assertion for CPU, chipset, and memory controllers. Use Value: ±1.5% threshold accuracy prevents premature or delayed resets; latching OV output halts system on catastrophic overvoltage before damage occurs. |
Use Scenario: Supervising redundant 12V, 5V, 3.3V, and –12V supplies in blade server backplanes. IC Role / Device Role / Timing Role: Simultaneous detection of undervoltage on positive rails and overvoltage on negative rails using SEL-configured inputs. Use Value: Buffered 1V REF enables accurate –12V monitoring with 3-resistor divider; 62µA ICC minimizes standby power impact across hundreds of nodes. |
| Core Voltage Monitors | I/O Voltage Monitors |
|
Use Scenario: Guarding FPGA or ASIC core supplies (e.g., 1.2V, 0.9V) against droop during high-current transients. IC Role / Device Role / Timing Role: High-accuracy comparator pair detecting sub-50mV deviations from nominal, with 50µs response delay. Use Value: Guaranteed ±1.5% accuracy over –40°C to +85°C ensures consistent trip points across thermal zones; TMR timeout prevents chatter during marginal recovery. |
Use Scenario: Validating PCIe slot 3.3V, SATA 5V, USB 5V, and DDR termination voltages in storage controllers. IC Role / Device Role / Timing Role: Common UV/OV outputs drive shared reset tree for multiple I/O subsystems with synchronized release timing. Use Value: Open-drain outputs support wired-OR reset bus; weak internal pull-up eliminates need for external resistors on low-speed control lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad voltage monitor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC2914IDHC-2#PBF | LTC2914-2 variant: replaces LATCH with DIS pin to disable both UV/OV outputs; no latching OV functionality. | Suitable where system-level reset coordination requires software-controlled suppression of fault signals, not hardware latching. | Select LTC2914IDHC-2#PBF only if latching OV is unnecessary and output disable capability is required. |
| TPS3307-33DGNR | Triple-channel supervisor (not quad); fixed 3.3V UV threshold; no negative rail support; no adjustable timeout. | Limited to simpler 3-rail systems with only positive supplies; lacks polarity flexibility and precision timing control. | Choose TPS3307-33DGNR only for cost-sensitive, lower-complexity designs with exactly three 3.3V rails and no negative monitoring needs. |
Compared with LTC2914IDHC-2#PBF, the LTC2914IDHC-1#PBF provides hardware-enforced fault persistence via OV latch, while TPS3307-33DGNR sacrifices channel count, accuracy, and configurability for lower unit cost and smaller footprint.
Availability
LTC2914IDHC-1#PBF is available at Aetrix Electronics and suitable for desktop computers, network servers, and industrial embedded systems requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature grade (–40°C to +85°C).
Supply support for LTC2914IDHC-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.
The LTC2914 product line was developed specifically for space-constrained, multi-rail power supervision in computing and communications infrastructure, emphasizing accuracy, low power, and flexible polarity configuration.
FAQ
What is the operating temperature range for the LTC2914IDHC-1#PBF?
The LTC2914IDHC-1#PBF is rated for –40°C to +85°C (industrial grade), verified across all electrical specifications including ±1.5% threshold accuracy, 62µA quiescent current, and 6–14ms timeout range. This range is confirmed in the Absolute Maximum Ratings and Electrical Characteristics tables of the official datasheet.
How does the SEL pin configure polarity for negative voltage monitoring on the LTC2914IDHC-1#PBF?
When the SEL pin is tied to GND, inputs VH3/VL3 and VH4/VL4 are configured for negative supply monitoring: VHn triggers OV when below 0.5V, and VLn triggers UV when above 0.5V. This allows direct monitoring of rails like –5V or –12V using the buffered 1V REF and a 3-resistor divider - no external level-shifting circuitry is needed.
What is the function of the LATCH pin on the LTC2914IDHC-1#PBF?
The LATCH pin on the LTC2914IDHC-1#PBF controls the overvoltage output behavior: pulling it low causes OV to latch low upon any overvoltage event, holding reset until LATCH is pulled high. When held high, OV behaves identically to UV - asserting low during faults and releasing after the TMR timeout expires. This latching is exclusive to the LTC2914-1 variant.
Can the LTC2914IDHC-1#PBF monitor voltages above 6V?
Yes - the LTC2914IDHC-1#PBF includes an internal 6.6V shunt regulator on the VCC pin. To monitor supplies >6V, connect the source through a series current-limiting resistor to keep VCC pin current ≤10mA. The device then operates as a shunt-regulated supply, maintaining internal bias while drawing only 62µA quiescent current from the regulated node.
What is the purpose of the TMR pin on the LTC2914IDHC-1#PBF?
The TMR pin sets the UV/OV timeout period: connecting a capacitor (e.g., 1nF) between TMR and GND yields a 6–14ms delay (temperature-dependent) that holds UV/OV asserted after all monitored rails return to valid range. This guarantees minimum reset pulse width for system stabilization. Tying TMR to VCC disables the timeout, causing immediate release upon fault clearance.
LTC2914IDHC-1#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 4
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- Adjustable/Selectable
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-DFN (5x3)
LTC2914IDHC-1#PBF FAQ
1.How can I place an order for LTC2914IDHC-1#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2914IDHC-1#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2914IDHC-1#PBF reliable?
The price and inventory of LTC2914IDHC-1#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2914IDHC-1#PBF is usually 5 days.
3.What payment methods are accepted for LTC2914IDHC-1#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2914IDHC-1#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2914IDHC-1#PBF?
LTC2914IDHC-1#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2914IDHC-1#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2914IDHC-1#PBF?
For technical support, including LTC2914IDHC-1#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2914IDHC-1#PBF requirements.
6.How does Aetrix verify that LTC2914IDHC-1#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2914IDHC-1#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2914IDHC-1#PBF meets industry standards.
7.What is the process for return or replacement of LTC2914IDHC-1#PBF?
All LTC2914IDHC-1#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2914IDHC-1#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2914IDHC-1#PBF part is unused and in its original packaging.
Return procedure for LTC2914IDHC-1#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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