Analog Devices Inc. LTC2919CDDB-3.3#TRMPBF
- Part No.:
- LTC2919CDDB-3.3#TRMPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC2919CDDB-3.3#TRMPBF.pdf
- Description:
- IC SUPERVISOR 3 CHANNEL 10DFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,847
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2919CDDB-3.3#TRMPBF from Analog Devices is a precision triple-input UV/OV monitor IC for system power supervision, featuring two 0.5V-threshold adjustable inputs with ±1.5% accuracy over 0°C to 70°C, a fixed 3.3V VCC UVLO (2.871V threshold), open-drain RST/OUT1/OUT2 outputs, and internal 200ms reset timeout - deployed in desktop computers, network servers, and automotive core/I/O monitoring.
For engineers reviewing the LTC2919CDDB-3.3#TRMPBF datasheet, LTC2919CDDB-3.3#TRMPBF pinout, LTC2919CDDB-3.3#TRMPBF application, or LTC2919CDDB-3.3#TRMPBF equivalent, this page delivers verified electrical parameters, polarity-selectable dual-input monitoring logic, glitch-filtered timing behavior, and DFN-10 package integration guidance for reliable supply fault detection in space-constrained embedded systems.
Technical Context
The LTC2919CDDB-3.3#TRMPBF implements dual independent voltage comparators with user-configurable input polarity (via three-state SEL pin), each referenced to a tightly specified 495–505 mV threshold, and a third dedicated VCC UVLO comparator set for 3.3V nominal supply (2.871–2.970 V trip range). All thresholds maintain ±1.5% accuracy across 0°C to 70°C.
Its reset architecture combines propagation delay filtering (50–800 µs) and configurable timeout (internal 200ms, external capacitor, or disabled), with open-drain outputs guaranteed low down to VCC = 0.5V. The buffered 1.000V reference (±10 mV, ±1 mA load) enables negative-supply offset monitoring without external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC UVLO Threshold | 2.871 V (min), 2.921 V (typ), 2.970 V (max) - precise -10% trip point for 3.3V supply monitoring |
| ADJ Input Threshold | 495.0–505.0 mV - 0.5V nominal with ±1.5% full-temperature accuracy for dual adjustable inputs |
| Quiescent Current | 50 µA (typ), ≤220 µA (max at 70°C) - enables micropower operation in always-on supervision circuits |
| Reset Timeout | 200 ms (internal, TMR = GND) - factory-trimmed timer eliminates external RC component for deterministic release |
| Output Type | Open-drain RST, OUT1, OUT2 - supports level-shifting, wired-OR, and pull-up to voltages > VCC (up to 7.5V) |
| Reference Output | 0.990–1.010 V (±10 mV), ±1 mA sourcing/sinking - stable 1V buffer for negative-rail offset generation |
| Operating Temp | 0°C to 70°C (C-grade) - qualified for commercial and industrial control applications with defined thermal margin |
Pinout & Package
Package: 10-lead (3 mm × 2 mm) plastic DFN with exposed pad (DDB); RoHS-compliant, lead-free finish; thermal resistance θJA = 76°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SEL (Pin 1) | Three-state polarity select | Configures ADJ1/ADJ2 as (+)UV/(–)OV, (+)UV/(–)UV, or (–)UV/(–)OV - no external components required |
| VCC (Pin 2) | Power supply input | Operates directly up to 6V; includes 6.5V shunt regulator for high-voltage operation with series resistor |
| OUT1 (Pin 3) | Adjustable input 1 status output | Asserts low when ADJ1 violates configured polarity threshold - open-drain, supports >VCC pull-up |
| OUT2 (Pin 4) | Adjustable input 2 status output | Asserts low when ADJ2 violates configured polarity threshold - independent of OUT1 and RST |
| RST (Pin 5) | System reset output | Inverted open-drain output released only after both ADJ inputs and VCC are valid for full timeout period |
| GND (Pin 6) | Ground reference | Primary return path for all analog and digital circuitry; exposed pad may be tied to GND for thermal improvement |
| REF (Pin 7) | Buffered 1V reference | Stable 1.000V output for generating negative-supply monitor offsets; drives up to 1 mA with <1000 pF load |
| TMR (Pin 8) | Reset timeout control | GND = 200ms internal timeout; open = ~400µs min; VCC = comparator mode (no timeout); capacitor = programmable delay |
| ADJ2 (Pin 9) | Adjustable input 2 | 0.5V threshold comparator input; polarity set by SEL; tie to GND if unused (with SEL = GND or OPEN) |
| ADJ1 (Pin 10) | Adjustable input 1 | 0.5V threshold comparator input; polarity set by SEL; tie to REF if unused (with SEL = VCC or OPEN) |
Key Features
| Feature | Design Value |
|---|---|
| Polarity-selectable dual inputs | SEL pin configures ADJ1/ADJ2 for positive/negative UV/OV detection without external resistors or switches |
| Triple independent monitoring | Simultaneous supervision of two adjustable supplies + fixed 3.3V VCC UVLO - eliminates need for multiple discrete supervisors |
| Glitch-immune timing | Propagation delay filtering (50–800 µs) + programmable timeout prevents false resets from transient noise or load spikes |
| Micropower operation | 50 µA typical ICC enables battery-backed or energy-harvesting applications without compromising accuracy |
| Robust low-VCC operation | Outputs guaranteed low down to VCC = 0.5V - ensures deterministic reset assertion during brownout and power-up sequencing |
Applications
| Desktop Power Sequencing | Automotive I/O Monitoring |
|---|---|
|
Use Scenario: Supervising 3.3V core rail and 1.8V DDR termination voltage in compact desktop motherboards with tight layout constraints. IC Role / Device Role / Timing Role: LTC2919CDDB-3.3#TRMPBF acts as primary triple-supply supervisor, using ADJ1 for 1.8V (via resistor divider), ADJ2 for auxiliary 5V, and VCC UVLO for main 3.3V rail. Use Value: Single-chip solution replaces three discrete supervisors, reducing BOM count and PCB area while maintaining ±1.5% threshold accuracy across temperature. |
Use Scenario: Monitoring 3.3V microcontroller supply and isolated CAN transceiver bias in automotive body control modules. IC Role / Device Role / Timing Role: LTC2919CDDB-3.3#TRMPBF provides fail-safe reset via RST output, with ADJ1 tracking 3.3V MCU rail and ADJ2 monitoring isolated 5V CAN bias under reverse-battery conditions. Use Value: SEL pin enables negative-polarity configuration on ADJ2 to detect overvoltage on isolated rail without additional level-shifting circuitry. |
| Network Server Core Monitor | Industrial PLC Power Validation |
|
Use Scenario: Validating 3.3V FPGA configuration voltage and 12V auxiliary supply in 1U rack-mounted servers requiring high reliability. IC Role / Device Role / Timing Role: LTC2919CDDB-3.3#TRMPBF uses internal 200ms timeout (TMR = GND) to ensure clean power-up before releasing RST to FPGA, while OUT1/OUT2 provide per-rail fault flags to BMC. Use Value: Factory-trimmed timeout eliminates timing drift from capacitor aging or temperature variation, improving long-term system uptime. |
Use Scenario: Detecting undervoltage on 24V DC field bus and 5V logic rail in DIN-rail mounted programmable logic controllers operating in harsh industrial environments. IC Role / Device Role / Timing Role: LTC2919CDDB-3.3#TRMPBF monitors 24V bus via ADJ1 (using REF-based offset) and 5V rail via ADJ2, with RST holding CPU in reset until both stabilize. Use Value: Buffered 1V REF enables accurate negative-offset scaling for 24V monitoring - eliminating need for precision op-amps or matched resistor networks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar supply monitoring applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6816EUT+T | Single 3.3V UVLO only; no adjustable inputs or REF output; 5-pin SOT23 package | Supports basic 3.3V rail monitoring only - cannot replace dual-adjustable functionality of LTC2919CDDB-3.3#TRMPBF | Select only when supervising one fixed supply with minimal footprint and cost constraints |
| TPS3808G33DBVR | Single 3.3V supervisor with 200ms timeout; no dual inputs, no polarity selection, no REF output; 6-pin SOT23 | Lacks ADJ1/ADJ2 flexibility and negative-monitoring capability - suitable only for simple single-rail reset generation | Choose when system requires only VCC UVLO with factory-set delay and no secondary supply supervision |
Compared with MAX6816EUT+T and TPS3808G33DBVR, the LTC2919CDDB-3.3#TRMPBF delivers triple-input supervision, polarity configurability, and buffered reference in a single DFN-10 package - enabling consolidated fault detection where multi-rail validation and negative-supply support are essential.
Availability
LTC2919CDDB-3.3#TRMPBF is available at Aetrix Electronics and suitable for desktop computers, network servers, and automotive core/I/O monitoring requiring stable component supply, consistent parametric performance, and long-term production continuity.
Supply support for LTC2919CDDB-3.3#TRMPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2919 product line delivers precision, low-power, multi-input voltage supervisors optimized for reliable power-up sequencing, brownout protection, and fault logging in space-constrained embedded systems.
FAQ
What is the exact VCC UVLO threshold for LTC2919CDDB-3.3#TRMPBF?
The LTC2919CDDB-3.3#TRMPBF has a guaranteed VCC UVLO threshold of 2.871 V (minimum), 2.921 V (typical), and 2.970 V (maximum) - corresponding to –10% of 3.3V with ±1.5% tolerance over 0°C to 70°C. This value is factory-trimmed and applies specifically to the -3.3 variant; other variants (e.g., -2.5, -5) have different UVLO points.
Can LTC2919CDDB-3.3#TRMPBF monitor negative voltages?
Yes, the LTC2919CDDB-3.3#TRMPBF can monitor negative supplies using its adjustable inputs (ADJ1/ADJ2) configured in negative polarity mode via the SEL pin. When SEL is grounded, both inputs detect undervoltage on negative rails (e.g., –5V) or overvoltage on positive rails. The buffered 1V REF output provides the necessary offset for accurate negative-rail scaling.
How does the TMR pin configure reset timeout on LTC2919CDDB-3.3#TRMPBF?
On the LTC2919CDDB-3.3#TRMPBF, tying TMR to GND selects the internal 200ms timeout; leaving TMR open yields ~400µs minimum; connecting TMR to VCC disables timeout (comparator mode); and adding a capacitor to GND sets timeout to 9ms/nF (e.g., 22nF → 200ms). The internal timer is factory-calibrated and requires no external components for standard use.
What is the maximum sink current supported by LTC2919CDDB-3.3#TRMPBF outputs?
The LTC2919CDDB-3.3#TRMPBF open-drain outputs (RST, OUT1, OUT2) guarantee VOL ≤ 0.15 V at 2500 µA sink current when VCC = 3V. At lower VCC (e.g., 0.5V), they maintain VOL ≤ 0.15 V with 5 µA sink. These values are measured across the full 0°C to 70°C range and ensure robust logic-level compatibility with diverse host systems.
Is LTC2919CDDB-3.3#TRMPBF pin-compatible with other LTC2919 variants?
Yes, all LTC2919 variants - including LTC2919CDDB-2.5#TRMPBF, LTC2919CDDB-5#TRMPBF, and temperature-grade versions - share identical DFN-10 (DDB) and MSOP-10 footprints and pinouts. Only the VCC UVLO threshold differs between -2.5, -3.3, and -5 variants; all other electrical and functional characteristics remain consistent across the family.
LTC2919CDDB-3.3#TRMPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 3
- Voltage - Threshold:
- 2.921V, Adj, Adj
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x2)
LTC2919CDDB-3.3#TRMPBF FAQ
1.How can I place an order for LTC2919CDDB-3.3#TRMPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2919CDDB-3.3#TRMPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2919CDDB-3.3#TRMPBF reliable?
The price and inventory of LTC2919CDDB-3.3#TRMPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2919CDDB-3.3#TRMPBF is usually 5 days.
3.What payment methods are accepted for LTC2919CDDB-3.3#TRMPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2919CDDB-3.3#TRMPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2919CDDB-3.3#TRMPBF?
LTC2919CDDB-3.3#TRMPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2919CDDB-3.3#TRMPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2919CDDB-3.3#TRMPBF?
For technical support, including LTC2919CDDB-3.3#TRMPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2919CDDB-3.3#TRMPBF requirements.
6.How does Aetrix verify that LTC2919CDDB-3.3#TRMPBF is sourced from the original manufacturer or authorized distributors?
All LTC2919CDDB-3.3#TRMPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2919CDDB-3.3#TRMPBF meets industry standards.
7.What is the process for return or replacement of LTC2919CDDB-3.3#TRMPBF?
All LTC2919CDDB-3.3#TRMPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2919CDDB-3.3#TRMPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2919CDDB-3.3#TRMPBF part is unused and in its original packaging.
Return procedure for LTC2919CDDB-3.3#TRMPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2919CDDB-3.3#TRMPBF Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

