Analog Devices Inc. LTC2919CDDB-5#TRPBF
- Part No.:
- LTC2919CDDB-5#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC2919CDDB-5#TRPBF.pdf
- Description:
- IC SUPERVISOR 3 CHANNEL 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2919CDDB-5#TRPBF from Analog Devices is a precision triple-input voltage supervisor IC for system power monitoring, featuring two 0.5V adjustable inputs with ±1.5% threshold accuracy over 0°C to 70°C, a fixed -10% VCC UVLO (4.35V nominal), open-drain RST/OUT1/OUT2 outputs, and configurable reset timeout (200ms internal or external capacitor-based). It supports positive/negative supply monitoring in desktop computers, network servers, and automotive core/I/O systems.
For engineers reviewing the LTC2919CDDB-5#TRPBF datasheet, LTC2919CDDB-5#TRPBF pinout, LTC2919CDDB-5#TRPBF application, or LTC2919CDDB-5#TRPBF equivalent, key selection criteria include its dual adjustable input polarity control via SEL pin, buffered 1V reference for negative-supply offset, 50µA quiescent current, 6.5V shunt regulator capability, and guaranteed low output behavior down to VCC = 0.5V.
Technical Context
The LTC2919CDDB-5#TRPBF implements dual independent comparator channels with user-selectable polarity (positive/negative UV/OV) via a three-state SEL pin, enabling flexible fault detection across mixed-polarity supplies. Its third monitoring channel uses an accurate VCC UVLO threshold of 4.35V (–10% of 5V) with 0.3–2.0% hysteresis.
Reset assertion is synchronized across all monitored inputs: RST remains low until both ADJ inputs and VCC are valid for the full timeout period (200ms internal or externally set). Glitch filtering on ADJ inputs and propagation delay vs. overdrive characteristics prevent false triggering from transient noise.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC UVLO Threshold | 4.35V (–10% of 5V supply); enables precise third-supply monitoring without external components |
| ADJ Input Threshold | 495–505mV (±1.5% over temp); supports accurate UV/OV detection for custom supply rails |
| Quiescent Current | 50µA typical; enables micropower operation in battery-backed or always-on monitoring circuits |
| Reset Timeout | 200ms internal (TMR = GND); eliminates need for external timing capacitor in standard applications |
| Output Type | Open-drain RST/OUT1/OUT2; allows level-shifting, wired-OR logic, and pull-up to voltages > VCC |
| Reference Output | 1.000V buffered REF (±10mV); provides stable offset for negative-supply monitoring networks |
| Supply Range | VCC = 0.5V to 6V; ensures reliable output pull-down during brownout and power-up sequences |
Pinout & Package
Package: 10-lead (3mm × 2mm) plastic DFN with exposed pad (DDB), rated for 0°C to 70°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SEL (Pin 1) | Three-state polarity select | Determines ADJ1/ADJ2 input polarity (positive UV/OV, negative UV/OV, or mixed) without external components |
| VCC (Pin 2) | Power supply input | Accepts 0.5–6V directly; includes internal 6.5V shunt regulator for high-voltage operation with series resistor |
| OUT1 (Pin 3) | Adjustable input 1 status output | Open-drain; asserts low when ADJ1 is invalid per selected polarity; requires external pull-up |
| OUT2 (Pin 4) | Adjustable input 2 status output | Open-drain; asserts low when ADJ2 is invalid per selected polarity; supports independent fault indication |
| RST (Pin 5) | System reset output | Open-drain; asserts low if any monitored input fails; held low for full timeout after recovery |
| GND (Pin 6) | Device ground | Reference for all analog and digital circuitry; exposed pad may be tied to GND for thermal improvement |
| REF (Pin 7) | Buffered 1V reference | Sources/sinks up to 1mA; used to bias resistive dividers for negative-supply monitoring |
| TMR (Pin 8) | Reset timeout control | GND = 200ms internal timeout; open = ~400µs min; VCC = comparator mode (no timeout) |
| ADJ2 (Pin 9) | Adjustable input 2 | 0.5V threshold comparator input; polarity set by SEL; tie to GND if unused (SEL = GND/Open) |
| ADJ1 (Pin 10) | Adjustable input 1 | 0.5V threshold comparator input; polarity set by SEL; tie to REF if unused (SEL = VCC/Open) |
Key Features
| Feature | Design Value |
|---|---|
| Polarity-selectable dual inputs | SEL pin configures ADJ1/ADJ2 as positive UV/OV, negative UV/OV, or mixed - enabling single-IC monitoring of +5V/-15V rails |
| Accurate VCC UVLO | 4.35V threshold (–10% of 5V) with ±0.0375V max error over temperature - eliminates need for external UV monitor on main supply |
| Glitch-immune timing | Propagation delay increases with overdrive margin; combined with 200ms timeout, rejects transients < 5Hz without sacrificing DC accuracy |
| Micropower operation | 50µA ICC at 5V - reduces standby power in always-on supervisory circuits and extends battery life in backup systems |
| Low-voltage output guarantee | RST/OUT1/OUT2 sink to ≤0.15V at VCC = 3V with 2.5mA load - ensures clean logic-low assertion even during brownout |
Applications
| Desktop Power Sequencing | Automotive I/O Monitoring |
|---|---|
|
Use Scenario: Monitoring +5V main rail and +3.3V auxiliary rail during cold boot and thermal stress in compact desktop motherboards. IC Role / Device Role / Timing Role: LTC2919CDDB-5#TRPBF acts as primary supervisor, asserting RST until both rails stabilize above thresholds for 200ms; OUT1/OUT2 provide per-rail fault isolation. Use Value: Eliminates discrete UVLO comparators and RC timers, reducing BOM count by 4–6 components while maintaining ±1.5% trip accuracy over 0°C–70°C. |
Use Scenario: Supervising +5V infotainment supply and –12V sensor bias rail in AEC-Q100-compliant vehicle ECUs under load dump and cold-crank conditions. IC Role / Device Role / Timing Role: LTC2919CDDB-5#TRPBF monitors both rails simultaneously using SEL = OPEN configuration; REF pin offsets ADJ2 for negative rail sensing. Use Value: Single-IC solution replaces dual discrete supervisors, cuts PCB area by 40%, and guarantees RST assertion down to VCC = 0.5V during cranking. |
| Network Server Core Voltage Monitor | Industrial PLC Power Integrity |
|
Use Scenario: Validating +5V CPU core and +1.8V memory rails in 1U rack servers where space and reliability are critical. IC Role / Device Role / Timing Role: LTC2919CDDB-5#TRPBF uses internal 200ms timeout (TMR = GND) to suppress noise-induced resets during hot-swap events. Use Value: 50µA quiescent current minimizes standby loss; open-drain outputs interface directly with 3.3V FPGA reset controllers without level shifters. |
Use Scenario: Ensuring clean startup of +5V controller and +24V field I/O in industrial programmable logic controllers operating at 85°C ambient. IC Role / Device Role / Timing Role: LTC2919CDDB-5#TRPBF leverages its 6.5V shunt regulator to accept 28V field supply via series resistor, eliminating external LDO. Use Value: Reduces thermal load by 120mW vs. LDO-based solution; ±1.5% threshold accuracy prevents nuisance resets during 10% line variation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS3808G33DBVR | Single 3.3V fixed UVLO; no adjustable inputs, no negative monitoring, no REF output | Only suitable for basic 3.3V rail supervision; cannot replace dual-rail or mixed-polarity monitoring | Select only when monitoring one fixed 3.3V supply with no need for polarity flexibility or reference output |
| MAX6816EUT+T | Quad 0.63V adjustable inputs; no VCC UVLO, no REF, higher 100µA ICC, MSOP-8 package | Lacks third-supply monitoring and buffered reference; less accurate (±2.5% threshold) and higher power | Choose only for quad-rail monitoring where 50µA ICC and ±1.5% accuracy are not required |
Compared with TPS3808G33DBVR and MAX6816EUT+T, the LTC2919CDDB-5#TRPBF uniquely integrates dual adjustable inputs with polarity selection, a precise VCC UVLO, and a 1V buffered reference - enabling compact, accurate monitoring of mixed-polarity supplies in space-constrained designs without external support components.
Availability
LTC2919CDDB-5#TRPBF is available at Aetrix Electronics and suitable for desktop computers, network servers, and automotive I/O systems requiring stable component supply, long-term lifecycle support, and AEC-Q100-compliant variants.
Supply support for LTC2919CDDB-5#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2919 product line delivers precision, low-power, multi-rail voltage supervision for mission-critical power integrity in computing, networking, and automotive electronics - emphasizing accuracy, configurability, and robustness over temperature.
FAQ
What is the VCC UVLO threshold for LTC2919CDDB-5#TRPBF?
The LTC2919CDDB-5#TRPBF has a fixed VCC undervoltage lockout threshold of 4.35V (–10% of 5V), specified with ±0.0375V max error over 0°C to 70°C. This enables direct monitoring of a 5V supply without external resistors, and the UVLO hysteresis is 0.3–2.0% to prevent chatter near the trip point. The threshold is factory-trimmed and does not require calibration.
How does the SEL pin configure input polarity on LTC2919CDDB-5#TRPBF?
The SEL pin on LTC2919CDDB-5#TRPBF selects ADJ1/ADJ2 polarity via three states: tied to VCC (both inputs positive UV/OV), tied to GND (both negative UV/OV), or left open (ADJ1 positive, ADJ2 negative). Each state sets comparator logic so that "undervoltage" means below 0.5V for positive polarity or above 0.5V for negative polarity - enabling detection of –UV or +OV faults on the same IC.
Can LTC2919CDDB-5#TRPBF monitor a negative supply like –12V?
Yes, LTC2919CDDB-5#TRPBF can monitor –12V using its REF pin (1.000V) and ADJ2 input. Configure SEL = GND to set ADJ2 for negative polarity, then connect a resistor divider from –12V to REF so ADJ2 = 0.5V at the –12V fault threshold. For example, a –12V UV threshold of –11.4V maps to ADJ2 = 0.5V when REF = 1.0V, enabling accurate –UV detection without external op-amps.
What is the minimum VCC voltage required for LTC2919CDDB-5#TRPBF to assert a valid low on RST?
LTC2919CDDB-5#TRPBF guarantees RST output voltage ≤ 0.15V at VCC = 3V with 2.5mA sink current, and ≤ 0.30V at VCC = 0.5V with 2.5mA load. This low-voltage pull-down capability ensures reliable reset assertion during brownout and power-up sequences, even when VCC dips below 1V - critical for preventing undefined logic states in downstream processors.
Does LTC2919CDDB-5#TRPBF support external capacitor-based reset timeout?
Yes, LTC2919CDDB-5#TRPBF supports external timeout via the TMR pin: connecting CTMR to GND sets tRST = 9ms/nF (e.g., 22nF → 200ms). However, for the LTC2919CDDB-5#TRPBF variant, tying TMR to GND activates the factory-trimmed 200ms internal timeout - eliminating capacitor tolerance drift and board space. External capacitors are optional for non-standard timeouts (e.g., 15ms with 1.67nF).
LTC2919CDDB-5#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 3
- Voltage - Threshold:
- 4.425V, Adj, Adj
- Output:
- Open Drain or Open Collector
- Reset:
- Active Low
- Reset Timeout:
- 140ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x2)
LTC2919CDDB-5#TRPBF FAQ
1.How can I place an order for LTC2919CDDB-5#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2919CDDB-5#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2919CDDB-5#TRPBF reliable?
The price and inventory of LTC2919CDDB-5#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2919CDDB-5#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2919CDDB-5#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2919CDDB-5#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2919CDDB-5#TRPBF?
LTC2919CDDB-5#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2919CDDB-5#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2919CDDB-5#TRPBF?
For technical support, including LTC2919CDDB-5#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2919CDDB-5#TRPBF requirements.
6.How does Aetrix verify that LTC2919CDDB-5#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2919CDDB-5#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2919CDDB-5#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2919CDDB-5#TRPBF?
All LTC2919CDDB-5#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2919CDDB-5#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2919CDDB-5#TRPBF part is unused and in its original packaging.
Return procedure for LTC2919CDDB-5#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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