Analog Devices Inc. LTC2923CMS#PBF
- Part No.:
- LTC2923CMS#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Power Supply Controllers, Monitors
- Package:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
LTC2923CMS#PBF.pdf
- Description:
- IC PWR SUPPLY CONTROLLER 10MSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC2923CMS#PBF from Analog Devices (formerly Linear Technology) is a dual-channel power supply tracking and sequencing controller IC designed to coordinate ramp-up/ramp-down of up to three DC/DC supplies without affecting stability or transient response. It operates from 2.9V to 5.5V, supports adjustable ramp rates via external capacitor, provides open-loop current mirroring to FB1/FB2 pins (±5% current mismatch), and integrates electronic circuit breaker protection for optional external N-channel FET. Used in FPGA, microprocessor, and server power systems requiring precise VCORE/VI/O supply coordination.
For engineers reviewing the LTC2923CMS#PBF datasheet, LTC2923CMS#PBF pinout, LTC2923CMS#PBF application, or LTC2923CMS#PBF equivalent, key selection considerations include its 10-lead MSOP package, 0°C to 70°C operating range, 10µA GATE drive current, 200mV short-circuit detection threshold, and compatibility with both resistor-based tracking and external FET–based master supply control.
Technical Context
The LTC2923CMS#PBF implements an open-loop tracking architecture using proprietary wide-range current mirrors that servo TRACK1/TRACK2 at 0.8V and replicate current into FB1/FB2 to force slave supply outputs to track a master signal-either RAMPBUF voltage (no FET) or external FET source voltage. Its internal 10µA current source charges/discharges the GATE pin to set ramp rate, while a charge pump ensures GATE reaches ≥5V above VCC for full enhancement of logic-level N-channel MOSFETs.
It features undervoltage lockout (2.5V threshold with 25mV hysteresis), ON-pin controlled startup/shutdown with 1.23V threshold and 75mV hysteresis, and fault latching that disables GATE until ON falls below 0.4V. The RAMPBUF pin delivers buffered low-impedance drive (≥2mA) to TRACK resistive dividers, isolating them from RAMP node during FET-off conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Supply Range | 2.9V to 5.5V - defines minimum input rail for reliable operation; UVLO triggers below 2.5V |
| GATE Drive Current | ±10µA - sets linear ramp rate of external capacitor or FET gate; enables precise timing control |
| TRACK/FB Current Mismatch | ±5% - limits tracking error between slave supplies under matched load conditions |
| Short-Circuit Detection Threshold | 200mV (VCC – RAMP) - triggers immediate 20mA GATE pull-down to protect series FET |
| ON Pin Threshold | 1.230V ±18mV - determines exact activation point for power sequencing initiation |
| RAMPBUF Output Drive | ≥2mA - sufficient to drive standard resistor networks on TRACK1/TRACK2 without droop |
| Operating Temperature | 0°C to 70°C - validated performance range for commercial-grade embedded and server applications |
Pinout & Package
Package: 10-Lead Plastic MSOP (MS package), 3mm × 3mm body, exposed pad (not electrically connected by default).
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| VCC (1) | Positive supply input | Power source for internal circuitry; requires 0.1µF bypass capacitor to GND |
| ON (2) | Sequencing enable control | Active-high input with 1.23V threshold; pulls 10µA from GATE to initiate ramp-up |
| TRACK1 (3) | Slave 1 tracking reference input | Servo'd at 0.8V; current mirrored to FB1 to control first slave supply output |
| TRACK2 (4) | Slave 2 tracking reference input | Servo'd at 0.8V; current mirrored to FB2 to control second slave supply output |
| RAMPBUF (5) | Buffered master ramp signal output | Low-impedance copy of RAMP; drives TRACKx resistive dividers without loading RAMP node |
| GND (6) | Circuit ground reference | Return path for all internal currents; must be low-impedance connection |
| FB2 (7) | Slave 2 feedback control output | Sinks current into slave 2 DC/DC feedback node to adjust output voltage per TRACK2 command |
| FB1 (8) | Slave 1 feedback control output | Sinks current into slave 1 DC/DC feedback node to adjust output voltage per TRACK1 command |
| GATE (9) | External N-channel FET gate driver | Supplies/sinks 10µA; includes charge pump to ensure ≥5V overdrive above VCC |
| RAMP (10) | Master ramp signal input/output | Connects to FET source (with external FET) or ties to GATE (no FET); monitored for short-circuit fault |
Key Features
| Feature | Design Value |
|---|---|
| Open-loop tracking architecture | Eliminates impact on slave supply loop stability and transient response-no compensation required |
| Adjustable ramp rate via external capacitor | 10µA current source enables precise, predictable ramp slopes (e.g., 1000 V/s with 10nF) |
| Electronic circuit breaker | Detects VDS > 200mV across external FET and pulls GATE low with 20mA within 20µs |
| RAMPBUF isolation | Prevents TRACKx pins from pulling up FET source when FET is off-ensures clean turn-off behavior |
| ON-pin hysteresis and fault reset | 75mV hysteresis prevents chatter; <0.4V ON input clears latched short-circuit fault |
Applications
| VCORE/VI/O Tracking in Microprocessors | FPGA Power Sequencing |
|---|---|
Use Scenario: Coordinating 1.2V core and 2.5V I/O rails during boot and shutdown to prevent latch-up in multi-rail ASICs. IC Role / Device Role / Timing Role: LTC2923CMS#PBF acts as master sequencer, forcing both rails to ramp simultaneously with zero voltage differential. Use Value: Eliminates need for discrete RC networks or dedicated sequencer ICs-reduces BOM count and layout area. |
Use Scenario: Ensuring configuration voltage (2.5V) ramps before core voltage (1.0V) in Xilinx/Altera FPGAs to meet device specification. IC Role / Device Role / Timing Role: LTC2923CMS#PBF controls third supply via external FET to create delayed master ramp, enabling strict sequencing order. Use Value: Achieves sub-millisecond delay accuracy without timing drift across temperature or voltage. |
| Server PSU Coordination | Communication System Power Management |
Use Scenario: Managing 12V, 5V, and 3.3V rails in telecom server PSUs where staggered startup avoids inrush current overload. IC Role / Device Role / Timing Role: LTC2923CMS#PBF configures offset tracking to maintain fixed voltage gaps (e.g., 5V rises 100ms after 12V) using RTA/RTB resistor network. Use Value: Enables compliance with EN 61000-3-2 harmonic current limits through controlled inrush profile. |
Use Scenario: Synchronizing DSP, RF transceiver, and memory supply ramps in 5G baseband units to minimize power-on glitches. IC Role / Device Role / Timing Role: LTC2923CMS#PBF uses ratiometric tracking mode to scale slave ramp rates (e.g., 1.8V at 600 V/s, 3.3V at 850 V/s) from single RAMPBUF source. Use Value: Guarantees all supplies reach regulation before clock distribution begins-prevents metastability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power supply tracking controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS652860RGER | Integrated triple-buck controller with built-in MOSFET drivers; no external FET needed for main rails; lacks RAMPBUF isolation and open-loop current mirror architecture | Targets compact, integrated PMIC designs; not suitable for retrofitting existing discrete DC/DC supplies | Choose TPS652860RGER when designing new board with co-located regulators; choose LTC2923CMS#PBF when reusing legacy DC/DC modules or requiring minimal footprint impact. |
| ADM1185ARMZ-REEL | Single-channel supervisor with programmable delay and reset; no tracking capability, no FB current mirroring, no GATE drive | Only provides basic power-good monitoring and reset assertion-not a functional substitute for tracking/sequencing | Use ADM1185ARMZ-REEL for simple POR/reset; use LTC2923CMS#PBF only when true analog tracking or multi-supply coordination is required. |
Compared with TPS652860RGER and ADM1185ARMZ-REEL, the LTC2923CMS#PBF uniquely delivers open-loop analog tracking of pre-existing DC/DC converters without modifying their feedback loops-enabling field-upgradeable sequencing in space-constrained systems where integration isn't feasible.
Availability
LTC2923CMS#PBF is available at Aetrix Electronics and suitable for FPGA power management, microprocessor VCORE/VI/O coordination, and server PSU sequencing requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for LTC2923CMS#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.
The LTC2923 belongs to Linear's precision power management product line, engineered specifically for analog-based power supply coordination in high-reliability computing and communications infrastructure where stability, predictability, and minimal design overhead are critical.
FAQ
What is the primary function of the LTC2923CMS#PBF in a power system?
The LTC2923CMS#PBF serves as a dual-channel analog power supply tracking and sequencing controller. It coordinates the ramp-up and ramp-down of up to three DC/DC supplies-two via direct FB pin current injection and a third via external N-channel FET driven by its GATE pin-without inserting pass elements or degrading stability. Its core function is to enforce precise voltage relationships (coincident, offset, ratiometric, or sequential) between supplies during power transitions.
Can the LTC2923CMS#PBF operate without an external FET?
Yes, the LTC2923CMS#PBF can operate without an external FET by tying the RAMP and GATE pins together and connecting an external capacitor between GATE and GND. In this configuration, the capacitor voltage becomes the master ramp signal, and RAMPBUF drives the TRACKx resistive dividers to control FB1/FB2 currents. This enables two-supply tracking with no added components beyond the capacitor and resistors-ideal for space-constrained applications.
How does the LTC2923CMS#PBF protect against short-circuit faults?
The LTC2923CMS#PBF monitors the voltage difference between VCC and the RAMP pin. When the external FET is fully enhanced (GATE > RAMP + 4.9V), it enables short-circuit detection. If VCC – RAMP exceeds 200mV for more than ~10µs, the IC immediately pulls the GATE pin low with 20mA, turning off the FET. The fault remains latched until the ON pin is pulled below 0.4V to clear the condition-preventing uncontrolled restarts.
What is the role of the RAMPBUF pin in LTC2923CMS#PBF circuits?
The RAMPBUF pin provides a low-impedance, buffered copy of the RAMP signal, capable of sourcing ≥2mA. It drives the resistive dividers connected to TRACK1 and TRACK2, ensuring accurate current mirroring even when high-value resistors are used. Critically, RAMPBUF isolates the TRACKx pins from the RAMP node-preventing TRACKx from inadvertently pulling up the FET source during turn-off, which could cause unintended conduction or slow discharge.
Does the LTC2923CMS#PBF affect the transient response of controlled DC/DC supplies?
No, the LTC2923CMS#PBF does not affect the transient response or stability of the controlled DC/DC supplies. Its open-loop current-mirror architecture injects controlled current into the feedback nodes (FB1/FB2) without altering the feedback loop's phase margin or gain characteristics. Once ramping completes and TRACKx current drops to zero, the LTC2923CMS#PBF presents high impedance and becomes effectively invisible to the slave supply's regulation loop.
LTC2923CMS#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Power Supply Controller, Sequencer
- Voltage - Input:
- -
- Voltage - Supply:
- 2.9V ~ 5.5V
- Current - Supply:
- -
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-MSOP
LTC2923CMS#PBF FAQ
1.How can I place an order for LTC2923CMS#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2923CMS#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2923CMS#PBF reliable?
The price and inventory of LTC2923CMS#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2923CMS#PBF is usually 5 days.
3.What payment methods are accepted for LTC2923CMS#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2923CMS#PBF transactions.
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4.How is shipping managed for LTC2923CMS#PBF?
LTC2923CMS#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2923CMS#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2923CMS#PBF?
For technical support, including LTC2923CMS#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2923CMS#PBF requirements.
6.How does Aetrix verify that LTC2923CMS#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2923CMS#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2923CMS#PBF meets industry standards.
7.What is the process for return or replacement of LTC2923CMS#PBF?
All LTC2923CMS#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2923CMS#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2923CMS#PBF part is unused and in its original packaging.
Return procedure for LTC2923CMS#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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