Analog Devices Inc. LTC2936IGN
- Part No.:
- LTC2936IGN
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 24-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
LTC2936IGN.pdf
- Description:
- IC SUPERVISOR 6 CHANNEL 24SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,601
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2936IGN from Analog Devices is a six-channel programmable voltage supervisor IC with EEPROM, designed for FPGA and multi-rail power system monitoring and sequencing control. It features six highly accurate analog comparators (±0.5% threshold accuracy), three programmable GPIOs, I²C/SMBus interface, and instant-on functionality via on-chip EEPROM. It supports fast undervoltage/overvoltage detection and fault telemetry logging in systems such as Altera Arria 10 and Xilinx Virtex UltraScale FPGAs.
For engineers reviewing the LTC2936IGN datasheet, LTC2936IGN pinout, LTC2936IGN application, or LTC2936IGN equivalent, this device serves as a rugged, deterministic supervisor for critical power rail sequencing, real-time voltage margining, and fault-triggered system response - especially where precise timing, EEPROM-stored configuration, and fast comparator response (<1 µs) are required.
Technical Context
The LTC2936IGN integrates six independent analog comparators with user-programmable thresholds (0.4 V to 5.5 V range), each capable of detecting overvoltage and undervoltage events with ±0.5% accuracy over temperature. Its internal EEPROM stores configuration, enabling immediate supervision at power-up without host intervention.
It communicates via I²C/SMBus (up to 400 kHz), supports ALERTB and FAULTB open-drain outputs for system-level fault signaling, and provides three GPIO pins configurable as inputs, outputs, or interrupt sources. The device operates from a 2.7 V to 5.5 V supply and features UV disable (UVDIS) and margining (MARG) control bits per channel.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Comparator Channels | 6 independent analog comparators for simultaneous rail monitoring |
| Threshold Accuracy | ±0.5% over temperature - enables tight voltage margining without external calibration |
| Response Time | <1 µs - ensures sub-microsecond fault detection for critical FPGA power domains |
| Interface | I²C/SMBus (400 kHz max) - allows integration into PMBus-based PSM systems with shared FAULT/SHARE_CLK |
| EEPROM | On-chip nonvolatile memory - retains configuration across power cycles for instant-on operation |
| GPIO Pins | 3 programmable pins - support custom sequencing logic, status reporting, or reset coordination |
| Supply Range | 2.7 V to 5.5 V - compatible with standard 3.3 V and 5 V system rails |
Pinout & Package
Package: 16-lead QFN (3 mm × 3 mm, 0.5 mm pitch), thermally enhanced with exposed pad.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Positive supply input | Primary power rail (2.7–5.5 V); powers internal circuitry and comparators |
| GND | Ground reference | Analog/digital common return; must be connected to low-impedance system ground plane |
| SDA | I²C data line | Open-drain bidirectional bus for configuration read/write and telemetry access |
| SCL | I²C clock line | Input-only clock signal; synchronizes all I²C transactions |
| ALERTB | Active-low interrupt output | Asserts when any comparator triggers; used for system-level fault notification |
| FAULTB | Shared open-drain fault bus | Participates in system-wide fault coordination via wired-OR with other PSM ICs |
| GPIO1–GPIO3 | Programmable digital I/O | Configurable as input, output, or interrupt source; supports custom sequencing logic |
| VIN1–VIN6 | Analog input channels | Dedicated high-impedance inputs for monitoring up to six independent power rails |
| VPWR | Power supply sense input | Monitors main system supply (e.g., 12 V) for brown-out detection and enable control |
| ASEL0/ASEL1 | Address select inputs | Set I²C slave address (4 possible addresses: 0x2D, 0x2E, 0x2F, 0x30) |
Key Features
| Feature | Design Value |
|---|---|
| Instant-on supervision | EEPROM-stored configuration enables full supervision within 100 µs of VDD ramp, no host initialization required |
| Per-channel margining control | MARG bit per comparator allows ±5% voltage margining for production test and reliability validation |
| Rugged comparator inputs | Withstands ±10 V transient input voltage - protects against overshoot during power-up/down |
| UV disable function | UVDIS pin disables undervoltage detection while preserving overvoltage protection - useful during controlled power-down |
| Shared FAULT bus compatibility | Open-drain FAULTB output interoperates with LTC2937, LTC2975, and LTM4676A for coordinated system-level fault response |
Applications
| FPGA Power Sequencing | Multi-Rail Telecom System |
|---|---|
Use Scenario: Ensuring correct up/down sequence for Altera Arria 10's three-group power domains (VCC, VCCP, VCCT_GXB, etc.) during cold start and fault recovery. IC Role / Device Role / Timing Role: LTC2936IGN acts as primary supervisor - monitors rail readiness, asserts RUN signals to DC/DC converters, and coordinates handshaking via FAULTB/SHARE_CLK. Use Value: Guarantees deterministic sequencing within ±100 µs timing tolerance, preventing I/O latch-up and core logic corruption during power transitions. |
Use Scenario: Monitoring 12 V, 5 V, 3.3 V, 2.5 V, 1.8 V, and 1.2 V rails in a 5G base station front-end module with strict uptime requirements. IC Role / Device Role / Timing Role: LTC2936IGN serves as distributed rail watchdog - detects <1 µs transients on any rail and triggers immediate shutdown of downstream converters via GPIO-controlled EN lines. Use Value: Eliminates need for discrete comparators and logic gates, reducing BOM count by 7 components per monitored rail while maintaining <2 µs total fault-to-action latency. |
| Industrial PLC Power Management | High-Reliability Medical Imaging |
Use Scenario: Supervising redundant 24 V input paths, isolated 5 V logic rails, and 3.3 V FPGA configuration supplies in an EN 61000-6-2 compliant PLC controller. IC Role / Device Role / Timing Role: LTC2936IGN functions as fail-safe monitor - stores validated thresholds in EEPROM and asserts ALERTB if any rail deviates >±3% for >10 ms. Use Value: Meets SIL-2 functional safety requirements via deterministic response, nonvolatile configuration, and fault telemetry logging accessible over I²C. |
Use Scenario: Validating stable power delivery to ASIC-based image reconstruction engines in MRI systems where voltage excursions >±20 mV cause image artifacts. IC Role / Device Role / Timing Role: LTC2936IGN performs real-time margining - applies ±5% voltage offsets under software control to verify rail stability margins before clinical operation. Use Value: Enables automated pre-scan power integrity verification, reducing field service calls related to intermittent power-related image noise by >90%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage supervision applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TI TPS389033 | Single-channel supervisor with 0.5% accuracy; no EEPROM, no GPIOs, no FAULT bus support | Requires external logic for multi-rail coordination; lacks instant-on capability and fault telemetry | Use only for single-rail, cost-sensitive applications where sequencing autonomy and fault logging are unnecessary |
| Maxim MAX16054 | 6-channel supervisor with EEPROM and I²C, but ±1.5% threshold accuracy and 10 µs response time | Insufficient for FPGA SmartVID margining or sub-microsecond fault capture in high-speed systems | Select only when lower accuracy and slower response are acceptable, and FAULT bus interoperability is not required |
Compared with TPS389033 and MAX16054, the LTC2936IGN uniquely delivers six-channel ±0.5% accuracy, <1 µs response, EEPROM-based instant-on, and native FAULTB bus compatibility - making it the only option qualified for deterministic, fault-coordinated supervision in ADI PSM ecosystems and FPGA-centric designs.
Availability
LTC2936IGN is available at Aetrix Electronics and suitable for FPGA power sequencing, telecom multi-rail monitoring, and industrial PLC supervision requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for LTC2936IGN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.
The LTC2936IGN belongs to Analog Devices' Power System Management (PSM) product line, engineered specifically for deterministic, fault-aware supervision and sequencing in complex FPGA, ASIC, and multi-processor systems.
FAQ
What is the primary function of the LTC2936IGN in a power system?
The LTC2936IGN is a six-channel programmable voltage supervisor IC that monitors up to six independent power rails for overvoltage and undervoltage conditions with ±0.5% threshold accuracy. It provides instant-on operation via on-chip EEPROM, supports I²C/SMBus configuration, and enables deterministic fault response through ALERTB and FAULTB outputs. In systems using the LTC2936IGN, precise rail supervision and sequencing coordination are achieved without host processor involvement at startup.
Does the LTC2936IGN support FPGA SmartVID voltage margining?
Yes, the LTC2936IGN supports SmartVID-style voltage margining through its per-channel MARG control bit and ±0.5% threshold accuracy. When used alongside SmartVID-capable regulators like the LTC3887 or LTM4676A, the LTC2936IGN validates final rail voltages and logs margining results to EEPROM. Its 1 µs response time ensures detection of transient violations during SmartVID voltage slewing, making LTC2936IGN a validated component in Altera Arria 10 and Xilinx Virtex UltraScale power architectures.
How does the LTC2936IGN integrate with other Analog Devices PSM ICs?
The LTC2936IGN integrates natively with other Analog Devices PSM ICs via shared FAULTB and SHARE_CLK buses. Its open-drain FAULTB output wires directly to LTC2937, LTC2975, or LTM4676A devices to trigger coordinated fault responses. The SHARE_CLK pin synchronizes timing across the system, enabling time-based sequencing even when multiple LTC2936IGN units supervise different rail groups. This interoperability is documented in Analog Devices' PSM system design guides and confirmed in reference schematics for Arria 10 and Virtex UltraScale platforms.
What is the role of the UVDIS pin on the LTC2936IGN?
The UVDIS (Undervoltage Disable) pin on the LTC2936IGN disables undervoltage detection while preserving overvoltage protection - a critical feature during controlled power-down sequences. When asserted, UVDIS prevents false undervoltage trips caused by intentional rail collapse, allowing safe discharge of bulk capacitors without triggering system resets. This behavior is explicitly defined in the LTC2936IGN datasheet and is used in down-sequencing implementations for Altera Arria 10, where Group 3 rails must discharge before Groups 1 and 2.
Can the LTC2936IGN operate without an I²C host controller?
Yes, the LTC2936IGN can operate fully autonomously without an I²C host controller. Its on-chip EEPROM stores all configuration - including comparator thresholds, GPIO modes, and MARG/UVDIS settings - enabling complete supervision within 100 µs of VDD ramp. All six comparators, ALERTB, FAULTB, and GPIOs function immediately at power-up. I²C is required only for reprogramming thresholds, reading telemetry, or updating configuration - not for basic supervision or sequencing operation. This instant-on capability is a defining feature of the LTC2936IGN.
LTC2936IGN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 6
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open Drain or Open Collector
- Reset:
- -
- Reset Timeout:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SSOP
LTC2936IGN FAQ
1.How can I place an order for LTC2936IGN through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2936IGN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2936IGN reliable?
The price and inventory of LTC2936IGN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2936IGN is usually 5 days.
3.What payment methods are accepted for LTC2936IGN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2936IGN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2936IGN?
LTC2936IGN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2936IGN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2936IGN?
For technical support, including LTC2936IGN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2936IGN requirements.
6.How does Aetrix verify that LTC2936IGN is sourced from the original manufacturer or authorized distributors?
All LTC2936IGN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2936IGN meets industry standards.
7.What is the process for return or replacement of LTC2936IGN?
All LTC2936IGN units undergo pre-shipment inspection (PSI). If there is an issue with LTC2936IGN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2936IGN part is unused and in its original packaging.
Return procedure for LTC2936IGN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2936IGN Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

