Analog Devices Inc. LTC2953CDD-2#TRPBF
- Part No.:
- LTC2953CDD-2#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Power Supply Controllers, Monitors
- Package:
- 12-WFDFN Exposed Pad
- Datasheet:
-
LTC2953CDD-2#TRPBF.pdf
- Description:
- IC PB ON/OFF CONTROLLER 12DFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,027
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2953CDD-2#TRPBF from Analog Devices (formerly Linear Technology) is a push-button on/off controller with high-voltage open-drain enable output (⎯E⎯N), input/output supply monitoring, and microprocessor handshake capability. It operates from 2.7V to 27V, draws only 14μA quiescent current, features ±1.5% threshold accuracy, and supports 200ms reset timing via VM pin. It is used in battery-powered instrumentation and blade servers for orderly power sequencing.
For engineers reviewing the LTC2953CDD-2#TRPBF datasheet, LTC2953CDD-2#TRPBF pinout, LTC2953CDD-2#TRPBF application, or LTC2953CDD-2#TRPBF equivalent, key selection criteria include its high-voltage ⎯E⎯N output for PFET control, adjustable power-down timer (tPDT), UVLO lockout behavior, and 12-pin 3mm × 3mm DFN package with exposed pad.
Technical Context
The LTC2953CDD-2#TRPBF implements dual-function supply monitoring: an uncommitted power-fail comparator (PFI → ⎯P⎯F⎯O) and a latched under-voltage lockout (UVLO → ⎯I⎯N⎯T + EN release). Both comparators reference a precise 0.5V internal bandgap and operate independently of push-button state.
Its control logic includes a 32ms push-button debounce (tDB,ON/tDB,OFF), 512ms ⎯K⎯I⎯L⎯L turn-on blanking window, fixed 64ms internal power-down delay (tPD,Min), and capacitor-adjustable additional delay (tPDT = 6.4s/μF at PDT pin). The ⎯E⎯N output is active-low and rated to 50V, enabling direct control of external high-side PFETs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.7V to 27V - supports wide-input industrial and battery systems without external regulation. |
| Quiescent Current | 14μA typical - enables multi-year operation in always-on battery-supervised applications. |
| Enable Output Type | Open-drain ⎯E⎯N (active-low, 50V max) - directly drives gate of external high-side PFET for power path switching. |
| VM Reset Threshold | 0.5V ±1.5% - accurate voltage supervisor with 200ms reset timeout after VM rises above threshold. |
| UVLO Falling Threshold | 0.5V ±1.5% - initiates interrupt and eventual power-off when input drops below this level for >32ms. |
| PDT Timing Range | 64ms (default) to >10s (with external cap) - configurable failsafe power-down delay for unresponsive μP scenarios. |
| ESD Rating (⎯P⎯B) | ±10kV HBM - robust front-end for mechanical push-button interfaces in harsh environments. |
Pinout & Package
Package: 12-lead 3mm × 3mm plastic DFN (DD) with exposed thermal pad (Pin 13), RoHS-compliant, tape-and-reel (TRPBF).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Pin 1) | Ground reference | Primary analog/digital return; exposed pad may be connected to PCB ground for thermal relief. |
| VM (Pin 2) | Voltage monitor input | Compares against 0.5V reference; asserts ⎯R⎯S⎯T low if <0.5V and holds low for 200ms after recovery. |
| ⎯K⎯I⎯L⎯L (Pin 3) | Microprocessor kill input | 0.6V threshold; forces ⎯E⎯N release when pulled low; ignored during 512ms turn-on blanking period. |
| PDT (Pin 4) | Power-down timer capacitor node | Sets additional delay (tPDT) before ⎯E⎯N release; tPDT ≈ 6.4s/μF; open = 64ms default. |
| ⎯P⎯B (Pin 5) | Push-button input | Internal 100kΩ pull-up to 1.9V; debounced 32ms ON/OFF; ±10kV HBM rated; accepts up to 27V externally. |
| VIN (Pin 6) | Main supply input | 2.7V–27V operating range; powers internal circuitry and supplies bias for high-voltage outputs. |
| UVLO (Pin 7) | Under-voltage lockout input | 0.5V threshold; triggers ⎯I⎯N⎯T interrupt and eventual ⎯E⎯N release; locks out ⎯P⎯B if <0.5V during startup. |
| PFI (Pin 8) | Power-fail comparator input | 0.5V falling threshold with 4mV hysteresis; controls ⎯P⎯F⎯O independently; <10nA leakage. |
| ⎯P⎯F⎯O (Pin 9) | Power-fail open-drain output | Active-low, 50V-rated; asserts when PFI <0.5V; high-impedance otherwise; no internal pull-up. |
| ⎯R⎯S⎯T (Pin 10) | Reset open-drain output | Active-low, 10V-rated; asserts when VM <0.5V; held low for 200ms after VM recovers. |
| ⎯E⎯N (Pin 11) | Enable output (LTC2953-2) | Active-low, 50V-rated open-drain; drives external PFET gate; released high upon valid shutdown sequence. |
| ⎯I⎯N⎯T (Pin 12) | Interrupt open-drain output | Active-low, 10V-rated; debounced pulse (32–54.5ms) signaling push-button or UVLO event to μP. |
Key Features
| Feature | Design Value |
|---|---|
| High-voltage ⎯E⎯N output | 50V-rated open-drain enables direct control of external PFETs for power path switching without level-shifting. |
| Adjustable power-down timer | Capacitor-programmable tPDT (6.4s/μF) adds failsafe delay beyond fixed 64ms, preventing premature shutdown. |
| UVLO lockout during startup | Prevents system power-on when VIN is insufficient (<0.5V at UVLO pin), avoiding unstable brown-out operation. |
| 200ms VM reset with accuracy | Guaranteed ±1.5% threshold tolerance and 200ms timeout ensure reliable μP reset timing across temperature. |
| μP handshake protocol | 512ms ⎯K⎯I⎯L⎯L blanking window enforces proper boot sequence; KILL low forces immediate power-off. |
Applications
| Battery-Powered Instrumentation | Blade Server Power Management |
|---|---|
Use Scenario: Portable test equipment powered by Li-ion battery pack with dual-voltage supervision. IC Role / Device Role / Timing Role: LTC2953CDD-2#TRPBF monitors battery voltage via UVLO and PFI, controls main PFET power path via ⎯E⎯N, and signals low-battery warning via ⎯P⎯F⎯O. Use Value: Enables early battery warning (PFI) and graceful shutdown (UVLO + tPDT), extending usable runtime and preventing data loss. |
Use Scenario: Hot-swap power control in modular server chassis with redundant 12V inputs. IC Role / Device Role / Timing Role: LTC2953CDD-2#TRPBF acts as centralized power sequencer-accepting front-panel button press, asserting ⎯E⎯N to enable DC/DC, and coordinating μP-initiated shutdown via ⎯K⎯I⎯L⎯L. Use Value: Eliminates need for discrete logic and timers; ensures consistent power-up/down timing and fault isolation across modules. |
| Notebook Computer System Power | Industrial PLC I/O Module |
Use Scenario: Main system power enable in ultra-thin notebook with constrained board space and battery backup. IC Role / Device Role / Timing Role: LTC2953CDD-2#TRPBF replaces discrete MOSFET + RC + comparator solution; uses VM pin for 3.3V rail reset and ⎯E⎯N to drive high-side PFET for 5V/12V distribution. Use Value: Reduces BOM count by 7+ components; achieves 200ms reset compliance and <14μA standby current. |
Use Scenario: Field-replaceable I/O module requiring safe hot-insertion and controlled power ramp. IC Role / Device Role / Timing Role: LTC2953CDD-2#TRPBF manages module power via front-panel button and supervises 24V input via UVLO; ⎯I⎯N⎯T alerts host controller of user-initiated shutdown. Use Value: Provides deterministic 32ms interrupt pulse and 64ms+ configurable power-down, meeting IEC 61000-4-2 and functional safety timing requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar push-button power control applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS3808G33DBVR | Fixed 3.3V reset IC with manual reset input; no push-button debounce, no UVLO/PFI dual monitoring, no adjustable power-down timer. | Only provides basic reset supervision; lacks integrated power-path control and μP handshake logic. | Select when only reset timing and simple manual reset are required-no system power toggling capability. |
| MAX16054ATA+ | 3-channel supervisor with watchdog and programmable reset timeout; no push-button interface, no high-voltage enable output, no UVLO lockout. | Designed for complex multi-rail sequencing-not for front-panel power control or battery fail-safe shutdown. | Select for multi-voltage rail monitoring with watchdog; not suitable as direct replacement for LTC2953CDD-2#TRPBF's power-path role. |
Compared with TPS3808G33DBVR and MAX16054ATA+, the LTC2953CDD-2#TRPBF uniquely integrates push-button interface, high-voltage ⎯E⎯N output for PFET control, dual-supply monitoring (PFI + UVLO), and configurable power-down timing-making it the only option that fully implements a self-contained, μP-handshaked power-on/off controller in a single 3mm × 3mm package.
Availability
LTC2953CDD-2#TRPBF is available at Aetrix Electronics and suitable for battery-powered instrumentation, blade server power management, and industrial PLC I/O modules requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for LTC2953CDD-2#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, formed through the acquisition of Linear Technology in 2017.
The LTC2953 product line was designed specifically for intelligent, push-button-initiated power sequencing in space-constrained, battery-sensitive, and high-reliability systems-emphasizing low quiescent current, accurate voltage thresholds, and robust μP handshaking.
FAQ
What is the function of the ⎯E⎯N pin on the LTC2953CDD-2#TRPBF?
The ⎯E⎯N pin on the LTC2953CDD-2#TRPBF is an active-low, high-voltage (50V max) open-drain enable output. It directly controls the gate of an external high-side PFET to switch system power on/off. Unlike the LTC2953-1's EN (active-high), the LTC2953CDD-2#TRPBF's ⎯E⎯N asserts low to turn on power and releases high to shut down-enabling efficient power path design without level shifters.
How does the LTC2953CDD-2#TRPBF handle undervoltage conditions during startup?
The LTC2953CDD-2#TRPBF prevents system power-on when the UVLO pin voltage falls below 0.5V (±1.5%) by locking out the ⎯P⎯B input. This UVLO lockout ensures the device will not assert ⎯E⎯N unless the input supply is sufficiently stable-avoiding erratic behavior or brown-out operation during cold start or weak battery conditions.
Can the LTC2953CDD-2#TRPBF be used without a microprocessor?
Yes-the LTC2953CDD-2#TRPBF supports autonomous operation: push-button presses directly toggle ⎯E⎯N and generate debounced ⎯I⎯N⎯T pulses. However, full functionality-including safe power-down coordination and aborted-startup detection-requires connecting ⎯K⎯I⎯L⎯L to a μP or logic circuit that drives it high within 512ms of power-on and low to initiate shutdown.
What is the purpose of the PDT pin on the LTC2953CDD-2#TRPBF?
The PDT pin on the LTC2953CDD-2#TRPBF sets an adjustable delay (tPDT) before the ⎯E⎯N output is released during forced power-down. By connecting an external capacitor (e.g., 1500pF yields ~11.5ms), users extend the default 64ms internal delay, ensuring sufficient time for μP housekeeping before power removal-even if the processor fails to respond to the ⎯I⎯N⎯T interrupt.
Does the LTC2953CDD-2#TRPBF provide independent reset and power-fail monitoring?
Yes-the LTC2953CDD-2#TRPBF provides three independent monitoring functions: VM pin drives ⎯R⎯S⎯T with 200ms reset timing; PFI pin drives ⎯P⎯F⎯O for real-time power-fail warning; and UVLO pin drives ⎯I⎯N⎯T + ⎯E⎯N release for controlled shutdown. Each uses the same 0.5V reference but operates with separate comparators, hysteresis, and timing-ensuring no functional coupling between reset, warning, and shutdown paths.
LTC2953CDD-2#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 12-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Applications:
- Push Button, On/Off Controller
- Voltage - Input:
- -
- Voltage - Supply:
- 2.7V ~ 27V
- Current - Supply:
- 14 µA
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-DFN (3x3)
LTC2953CDD-2#TRPBF FAQ
1.How can I place an order for LTC2953CDD-2#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2953CDD-2#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2953CDD-2#TRPBF reliable?
The price and inventory of LTC2953CDD-2#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2953CDD-2#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC2953CDD-2#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2953CDD-2#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2953CDD-2#TRPBF?
LTC2953CDD-2#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2953CDD-2#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2953CDD-2#TRPBF?
For technical support, including LTC2953CDD-2#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2953CDD-2#TRPBF requirements.
6.How does Aetrix verify that LTC2953CDD-2#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC2953CDD-2#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2953CDD-2#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC2953CDD-2#TRPBF?
All LTC2953CDD-2#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2953CDD-2#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2953CDD-2#TRPBF part is unused and in its original packaging.
Return procedure for LTC2953CDD-2#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2953CDD-2#TRPBF Tags

-
UC3845AD8TR
Texas Instruments

-
UC2843AD8TR
Texas Instruments

-
LM3880MFX-1AE/NOPB
Texas Instruments

-
LM3880MFX-1AA/NOPB
Texas Instruments

-
INA234AIYBJR
Texas Instruments

-
INA700AYWFR
Texas Instruments

-
LM3880MF-1AE/NOPB
Texas Instruments

-
LM3880MF-1AA/NOPB
Texas Instruments

-
LM3881MM/NOPB
Texas Instruments

-
UCC2802DTR
Texas Instruments

-
NCP4305DMTTWG
onsemi
-
INA237AIDGSR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

