Analog Devices Inc. LTC2964CUDC#PBF
- Part No.:
- LTC2964CUDC#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Supervisors
- Package:
- 20-WFQFN Exposed Pad
- Datasheet:
-
LTC2964CUDC#PBF.pdf
- Description:
- IC SUPERVISOR 4 CHANNEL 20QFN
- Quantity:
- Payment:

- Shipping:

Inventory:182
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC2964CUDC#PBF from Analog Devices is a quad configurable power supply supervisor IC with individual open-drain comparator outputs (OUT1–OUT4), ±0.5% threshold accuracy over temperature, 0°C to 70°C operating range, and 20-lead 3mm × 4mm QFN package. It monitors up to four supply rails-including 5V, 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 1V, or ±ADJ-and supports undervoltage, overvoltage, and negative voltage detection in high-reliability telecom and server systems.
For engineers reviewing the LTC2964CUDC#PBF datasheet, LTC2964CUDC#PBF pinout, LTC2964CUDC#PBF application, or LTC2964CUDC#PBF equivalent, key selection considerations include its per-channel real-time status outputs (no reset timeout delay), ±0.5% threshold accuracy across temperature, support for adjustable thresholds via 1% external resistors on PG1–PG4, and compatibility with margining via RDIS pin.
Technical Context
The LTC2964CUDC#PBF implements four independent voltage comparators with programmable thresholds selected via 4-bit ADC conversion of PG1–PG4 inputs referenced to a 1.195V buffered internal reference. Each channel supports 16 selectable thresholds-including fixed –4%/–6% options for standard rails and ±ADJ modes with 0.5V trip point-enabling simultaneous monitoring of heterogeneous supplies with no shared timing dependency.
Unlike the LTC2962/LTC2963 variants, the LTC2964CUDC#PBF omits watchdog functionality and integrated reset timeout logic; instead, OUT1–OUT4 provide immediate, unfiltered comparator states with weak 6µA internal pull-ups to VCC. The RST output remains available as a combined reset signal with user-configurable timeout (via RT capacitor or internal 200ms mode) and push-pull/open-drain operation selectable via DVCC voltage level.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.25V to 5.5V - powers all analog and digital circuitry; ensures reliable operation across common system rail voltages. |
| Threshold Accuracy | ±0.5% over –40°C to 125°C - guarantees tight supervision margins without derating, enabling relaxed power supply tolerance requirements. |
| RST Timeout Options | Adjustable via CRT capacitor (12ms/nF) or fixed 200ms internal timer - provides flexibility for system boot sequencing and brownout recovery timing. |
| OUT1–OUT4 Output Type | Open-drain with 6µA internal pull-up to VCC - delivers real-time per-rail status without propagation delay or timeout masking; supports external pull-up to higher logic supply. |
| Reference Voltage | 1.195V ±12mV (±1%) - stable, buffered bandgap reference used for PG input decoding and ±ADJ mode level shifting. |
| Monitor Input Bias Current | ±15nA in ±ADJ mode; 0.8–1.6MΩ input resistance otherwise - minimizes loading on sensitive power rails and enables high-impedance resistor programming. |
| Operating Temperature | 0°C to 70°C (C-grade) - validated for commercial industrial environments including network infrastructure and embedded computing. |
Pinout & Package
Package: 20-lead 3mm × 4mm plastic QFN (UDC package) with exposed pad (Pin 21), optional PCB ground connection. Thermal resistance θJA = 52°C/W, θJC = 6.8°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RDIS | Reset Disable Input | Logic-low assertion forces RST high regardless of monitor conditions - enables safe voltage margining without triggering system reset. |
| MR | Manual Reset Input | Pulled up internally to VCC with 10µA; falling edge asserts RST immediately - supports pushbutton or logic-controlled reset initiation. |
| DVCC | Digital Logic Supply | Configures RST output drive: GND = open-drain; ≥1.6V = push-pull to DVCC - allows interface compatibility with diverse logic families. |
| VCC | Analog/Digital Power Supply | Primary supply for internal circuitry and internal pull-ups on RST/OUT1–OUT4 - requires ≥0.1µF bypass capacitor to GND. |
| RST | Combined Reset Output | Open-drain (DVCC = GND) or push-pull (DVCC ≥ 1.6V); asserted low if any V1–V4 falls below threshold - provides system-wide reset coordination. |
| GND | Device Ground | Common reference for all analog and digital signals; exposed pad may be connected to PCB ground for improved thermal performance. |
| REF | Buffered Reference Output | 1.195V ±12mV, capable of sourcing/sinking ±1mA - used to bias external resistor dividers on PG1–PG4 for threshold selection. |
| PG1–PG4 | Threshold Programming Inputs | Accept ratiometric voltage (0–VREF) to select one of 16 thresholds per channel via internal 4-bit ADC - enables precise configuration with 1% resistors. |
| V1–V4 | Monitor Input Channels | High-impedance inputs supporting UV/OV/–ADJ modes; each independently configurable - allows mixed-rail supervision (e.g., 3.3V, 1.8V, –5V, +ADJ). |
| RT | Reset Timeout Capacitor Input | Connects external CRT to GND to set tRST = 12ms/nF; tie to VCC for fixed 200ms timeout - decouples reset timing from processor clock. |
| OUT1–OUT4 | Individual Comparator Outputs | Real-time open-drain status outputs reflecting instantaneous comparator state per channel - no reset timeout delay; usable for sequencers or discrete fault indication. |
Key Features
| Feature | Design Value |
|---|---|
| Per-channel real-time status outputs | OUT1–OUT4 deliver immediate comparator state without reset timeout masking - enables precise power sequencing and granular fault isolation. |
| ±0.5% threshold accuracy over temperature | Reduces required system voltage margin by up to 1% versus ±1% supervisors - relaxes power supply design constraints and improves transient tolerance. |
| 16 programmable thresholds per channel | Supports standardized rails (5V/3.3V/2.5V/1.8V/1.5V/1.2V/1V at –4% or –6%) plus ±ADJ mode - eliminates need for multiple discrete supervisors. |
| Configurable RST output drive | DVCC pin selects between open-drain (GND) and push-pull (≥1.6V) - ensures interoperability with 1.8V, 3.3V, and 5V logic domains without external level shifters. |
| Reset disable for margining | RDIS pin holds RST high during intentional under/over-voltage testing - enables safe validation of processor voltage limits without system crash. |
Applications
| Telecom Power Sequencing | Server Board Health Monitoring |
|---|---|
|
Use Scenario: Coordinating startup order of multiple DC/DC converters powering FPGAs, ASICs, and memory on a 48V intermediate bus architecture. IC Role / Device Role / Timing Role: LTC2964CUDC#PBF monitors VCCIO, VDDCORE, VDDQ, and auxiliary bias rails with independent OUT1–OUT4 outputs feeding a CPLD-based sequencer. Use Value: Real-time per-rail status enables dynamic adjustment of enable delays; ±0.5% accuracy prevents false resets during marginal load transients. |
Use Scenario: Detecting undervoltage faults across CPU core, memory, PCIe, and management controller rails in a dual-socket x86 server motherboard. IC Role / Device Role / Timing Role: LTC2964CUDC#PBF provides parallel fault reporting via OUT1–OUT4 to BMC I²C GPIO expander while RST drives main PCH reset line. Use Value: Individual outputs allow BMC to identify failed rail before full system reset; RST timeout ensures clean reboot after sustained fault clearance. |
| Industrial PLC Power Integrity | Automotive ADAS Domain Controller |
|
Use Scenario: Supervising isolated 24V, 5V, 3.3V, and 1.2V supplies in an IP67-rated programmable logic controller with extended temperature operation. IC Role / Device Role / Timing Role: LTC2964CUDC#PBF uses PG1–PG4 with 1% resistors to configure –4% thresholds; RDIS enables factory calibration without resetting firmware. Use Value: C-grade rating meets industrial ambient specs; ±0.5% accuracy ensures reliable operation despite wide input ripple and aging effects. |
Use Scenario: Monitoring redundant 5V, 3.3V, 1.8V, and –12V supplies in a radar/Ethernet domain controller requiring ASIL-B compliance evidence. IC Role / Device Role / Timing Role: LTC2964CUDC#PBF supervises primary and backup rails; OUT1–OUT4 feed safety MCU for diagnostic coverage; RST triggers fail-safe shutdown. Use Value: Independent outputs support dual-lockstep diagnostics; ±0.5% accuracy satisfies ISO 26262 voltage monitoring requirements for fault detection latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad voltage supervisor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX6816ESE+ | Quad supervisor with fixed 3.08V/2.93V/2.63V/2.32V thresholds; no programmability; 16-pin SOIC package. | Lacks per-channel configuration and ±ADJ mode; limited to predefined rails; no individual outputs. | Select when only standard 3.3V/2.5V/1.8V supervision is needed and board space permits SOIC. |
| TPS3307-33DGNR | Triple voltage supervisor with fixed 3.08V/2.93V/2.63V thresholds; includes manual reset and watchdog; 8-pin MSOP. | Only three channels; no individual outputs; no negative/adjustable monitoring capability. | Choose for cost-sensitive triple-rail systems where watchdog functionality is required and OUT1–OUT4 are unnecessary. |
Compared with MAX6816ESE+ and TPS3307-33DGNR, the LTC2964CUDC#PBF offers unique per-channel configurability, ±ADJ mode for overvoltage/negative rail monitoring, and real-time individual outputs-making it suitable for complex, multi-rail systems where flexibility and diagnostic granularity outweigh fixed-threshold simplicity.
Availability
LTC2964CUDC#PBF is available at Aetrix Electronics and suitable for telecom infrastructure, server board health monitoring, and industrial PLC power integrity applications requiring stable component supply, long-term lifecycle support, and guaranteed C-grade temperature performance.
Supply support for LTC2964CUDC#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC2964CUDC#PBF belongs to the LTC2962 family of configurable quad supervisors, designed specifically for high-accuracy, multi-rail power monitoring in mission-critical networking, computing, and control systems where reliability and precision are non-negotiable.
FAQ
What is the primary function of the LTC2964CUDC#PBF?
The LTC2964CUDC#PBF is a quad configurable power supply supervisor IC that monitors up to four independent voltage rails with ±0.5% threshold accuracy. Its defining feature is the provision of individual open-drain comparator outputs (OUT1–OUT4), delivering real-time status per channel without reset timeout delay-unlike the LTC2962/LTC2963 variants. It also provides a combined RST output with configurable timeout and supports margining via the RDIS pin. The LTC2964CUDC#PBF is optimized for telecom, server, and industrial applications demanding precise, granular power integrity monitoring.
How does the LTC2964CUDC#PBF differ from the LTC2963?
The LTC2964CUDC#PBF differs from the LTC2963 primarily in its output architecture and feature set: it replaces the LTC2963's watchdog functionality (WDI/WDO/WDS/WT) with four dedicated open-drain comparator outputs (OUT1–OUT4). While both share identical monitor accuracy, threshold programming (PG1–PG4), and RST behavior, the LTC2964CUDC#PBF omits all watchdog-related pins and logic. This makes the LTC2964CUDC#PBF ideal for applications needing per-rail status visibility and sequencing control, whereas the LTC2963 targets systems requiring watchdog timer supervision.
Can the LTC2964CUDC#PBF monitor negative voltages?
Yes, the LTC2964CUDC#PBF can monitor negative voltages using its –ADJ mode. In this mode, each channel (V1–V4) compares the input against a 0.5V reference; when the input is negative, the comparator output (OUTn or RST) asserts low. This is achieved by connecting the negative rail through an external resistive divider to shift the voltage into the valid input range. The datasheet confirms –ADJ mode operation for undervoltage monitoring of negative supplies, and the absolute maximum ratings specify V1–V4 inputs down to –0.3V, supporting robust implementation with proper scaling.
What is the role of the DVCC pin on the LTC2964CUDC#PBF?
The DVCC pin on the LTC2964CUDC#PBF configures the drive strength and logic swing of the RST output. When DVCC is grounded, RST operates as an open-drain output with a weak 6µA internal pull-up to VCC. When DVCC is connected to a voltage ≥1.6V (e.g., 3.3V), RST becomes an active push-pull output driven to DVCC levels-enabling direct interfacing with diverse logic families without external level shifters. DVCC must never be left floating; grounding or connecting to a valid supply is mandatory for correct RST behavior.
How is threshold programming implemented on the LTC2964CUDC#PBF?
Threshold programming on the LTC2964CUDC#PBF is performed via PG1–PG4 pins, each accepting a ratiometric voltage between 0V and the internal 1.195V REF output. A 4-bit ADC digitizes this voltage and selects one of 16 pre-calibrated thresholds per channel-including fixed –4% and –6% points for standard rails (5V, 3.3V, etc.) and ±ADJ modes. External 1% resistive dividers from REF to GND are recommended for precise setting; the datasheet provides optimal VPG/VREF ratios and standard resistor tables to achieve ±0.5% overall accuracy without trimming.
LTC2964CUDC#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- Multi-Voltage Supervisor
- Number of Voltages Monitored:
- 4
- Voltage - Threshold:
- Adjustable/Selectable
- Output:
- Open-Drain or Push-Pull
- Reset:
- Active Low
- Reset Timeout:
- 160ms Minimum
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN (3x4)
LTC2964CUDC#PBF FAQ
1.How can I place an order for LTC2964CUDC#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC2964CUDC#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC2964CUDC#PBF reliable?
The price and inventory of LTC2964CUDC#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC2964CUDC#PBF is usually 5 days.
3.What payment methods are accepted for LTC2964CUDC#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC2964CUDC#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC2964CUDC#PBF?
LTC2964CUDC#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC2964CUDC#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC2964CUDC#PBF?
For technical support, including LTC2964CUDC#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC2964CUDC#PBF requirements.
6.How does Aetrix verify that LTC2964CUDC#PBF is sourced from the original manufacturer or authorized distributors?
All LTC2964CUDC#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC2964CUDC#PBF meets industry standards.
7.What is the process for return or replacement of LTC2964CUDC#PBF?
All LTC2964CUDC#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC2964CUDC#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC2964CUDC#PBF part is unused and in its original packaging.
Return procedure for LTC2964CUDC#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC2964CUDC#PBF Tags

-
MIC826SYMT-TR
Microchip Technology

-
APX803S-31SA-7
Diodes Incorporated

-
APX803L20-29SA-7
Diodes Incorporated
-
TPS3828-33DBVR
Texas Instruments

-
V6340RSP3B+
EM Microelectronic

-
EM6325CXSP5B-2.9+
EM Microelectronic

-
MCP120T-300I/TT
Microchip Technology

-
MCP130T-315I/TT
Microchip Technology

-
MCP120T-475I/TT
Microchip Technology

-
MCP111T-300E/TT
Microchip Technology

-
MCP120T-315I/TT
Microchip Technology

-
MCP809T-315I/TT
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

