My Inquiry
My Account
Analog Devices Inc. LTC3110IFE#PBF
- Part No.:
- LTC3110IFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Battery Chargers
- Package:
- 24-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC3110IFE#PBF.pdf
- Description:
- IC BATT CHG SUPERCAP 24TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,092
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3110IFE#PBF from Analog Devices is a 2A bidirectional buck-boost DC/DC regulator and capacitor charger/balancer with 0.1V–5.5V VCAP and 1.8V–5.25V VSYS operating ranges, ±1% backup voltage accuracy, 1.2MHz fixed switching frequency, and 40μA Burst Mode quiescent current. It enables autonomous charge-to-backup switchover in supercapacitor-based backup systems for servers and RF infrastructure.
For engineers reviewing the LTC3110IFE#PBF datasheet, LTC3110IFE#PBF pinout, LTC3110IFE#PBF application, or LTC3110IFE#PBF equivalent, key selection criteria include bidirectional current capability, programmable ±2% charge current limit (125mA–2A), integrated VMID balancing buffer, open-collector status outputs (CAPOK/CHRG/CMPOUT), and thermal performance in –40°C to 125°C TSSOP-24 package.
Technical Context
The LTC3110IFE#PBF implements a proprietary low-noise switching algorithm that maintains continuous inductor current and stable VSYS regulation across VCAP voltages above, below, or equal to VSYS-enabling seamless mode transitions without output disruption. Its dual-mode control supports both fixed-frequency PWM (MODE = high) and Burst Mode (MODE = low) operation, with direction determined by DIR pin hysteresis (1.045V/1.095V thresholds).
It integrates a programmable current-sense amplifier (PROG pin), active voltage balancing at VMID (±150mA balancing current), end-of-charge supervision via FBVCAP (1.061V/1.095V thresholds), and four internal MOSFETs (SW1/SW2) with typical RDS(ON) of 49–86mΩ. Shutdown current is ≤1μA with VRUN = 0V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCAP Range | 0.1V to 5.5V - supports ultra-low-voltage supercapacitors and wide-capacity aging compensation |
| VSYS Range | 1.8V to 5.25V - matches common system rails including 3.3V and 5V microcontrollers and FPGAs |
| Max Output Current | 2A bidirectional - delivers full backup load current while maintaining <1% voltage regulation error |
| Backup Voltage Accuracy | ±1% - ensures reliable brown-out immunity for critical system components during power loss |
| Burst Mode IQ | 40μA - extends backup runtime in low-power standby without compromising wake-up response |
| Switching Frequency | Fixed 1.2MHz - enables compact 2.2µH inductor design and reduces EMI filtering requirements |
| Shutdown Current | ≤1μA - minimizes self-discharge in long-term storage or infrequent-use backup applications |
Pinout & Package
Package: 24-lead plastic TSSOP (FE), thermally enhanced, exposed PGND pad (Pin 25), –40°C to 125°C operating temperature range.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CAPOK (1) | VCAP OK indicator | Open-drain output pulled low when FBVCAP falls below 1.061V - signals undervoltage condition on backup capacitor stack |
| CMPOUT (2) | Comparator output | Open-drain output reflecting CMPIN comparison result - interfaces directly with µC GPIO for custom supervision logic |
| MODE (3) | Burst/PWM mode select | Logic high enables fixed-frequency PWM for max efficiency; logic low enables Burst Mode for lowest IQ at light loads |
| CMPIN (4) | Comparator input | Hysteresis-enabled analog input (0.59V/0.65V thresholds) - configurable as voltage supervisor or digital trigger |
| FBVCAP (5) | End-of-charge feedback | Programmable threshold input (1.061V rising / 1.095V falling) - sets final VCAP charge voltage with ±2% accuracy |
| SGND (6) | Signal ground | Dedicated low-noise analog reference - must be Kelvin-connected separately from PGND to avoid noise coupling |
| DIR (7) | Charge/backup mode select | Hysteresis input (1.045V/1.095V) - determines direction of power flow; enables autonomous switchover on power failure |
| RUN (8) | Enable/shutdown control | Logic-high (>1.0V) enables operation; ≤0.3V forces shutdown with <1μA supply current |
| FB (9) | VSYS feedback | 0.6V reference input - sets regulated VSYS output via external resistor divider (1.8V–5.25V range) |
| PROG (10) | Charge current programming | Resistor-to-SGND sets average IVSYS (125mA–2A) with 200µA/A gain - enables precise current limiting during charging |
| CHRG (11) | Charge mode indicator | Open-drain output low during charging - provides real-time status for system monitoring or LED indication |
| SVSYS (12) | Signal supply for controller | Must be tied to VSYS or filtered - powers internal bias circuitry independent of power path noise |
| VSYS (13,15) | Bidirectional system rail | Carries charge current into VCAP or backup current from VCAP - requires local 47µF ceramic bypass to PGND |
| RSEN (14) | Current sense tap | Connects to internal sense resistor - used for accurate current measurement and protection (max 1.6A DC) |
| SW2 (16,17) | Switch node C/D | Connects to one side of buck-boost inductor - high di/dt node requiring short, wide PCB trace to minimize ringing |
| PGND (18,19,25) | Power ground | High-current return path for switches and inductor - exposed pad (Pin 25) must be soldered for θJA = 33°C/W thermal performance |
| SW1 (20,21) | Switch node A/B | Connects to opposite side of buck-boost inductor - complementary high-side/low-side switching node |
| VCAP (22,23) | Bidirectional capacitor rail | Charges supercapacitors from VSYS or supplies backup power to VSYS - supports up to 5.5V with 0.1V start-up |
| VMID (24) | Capacitor balancing output | Active linear buffer regulating midpoint of series supercapacitors - prevents overvoltage on individual cells |
Key Features
| Feature | Design Value |
|---|---|
| Autonomous charge-to-backup switchover | Enables zero-intervention failover during main power loss using DIR pin hysteresis and internal state machine |
| Programmable ±2% charge current limit | Allows precise control of inrush and thermal stress during capacitor charging via single PROG resistor |
| Integrated VMID balancing buffer | Provides ±150mA active balancing current to equalize voltage across series supercapacitors without external ICs |
| 1.2MHz fixed-frequency PWM mode | Delivers low-noise, high-efficiency backup power with predictable EMI profile and minimal output ripple |
| 40μA Burst Mode quiescent current | Extends usable backup time in standby by minimizing self-consumption while preserving fast wake-up capability |
| Open-collector status outputs (CAPOK/CHRG/CMPOUT) | Directly drive µC GPIOs or discrete LEDs without level-shifting - simplifies system-level fault detection and logging |
Applications
| Server Backup Power | RAID System Capacitor Hold-Up |
|---|---|
Use Scenario: Maintaining NVRAM and controller state during AC mains interruption in enterprise servers. IC Role / Device Role / Timing Role: Bidirectional buck-boost regulator providing regulated 3.3V VSYS from 2.7V–5.5V supercapacitor stack (VCAP), with automatic switchover within microseconds. Use Value: Eliminates need for separate charger and backup ICs; ±1% VSYS accuracy prevents data corruption during brown-out conditions. | Use Scenario: Sustaining write-cache power in RAID controllers during unexpected power loss to prevent data loss. IC Role / Device Role / Timing Role: Charges two-series 10F supercapacitors to 5.4V during normal operation, then delivers 2A at 3.3V for ≥100ms hold-up time. Use Value: Integrated VMID balancing ensures no single capacitor exceeds 2.75V rating, extending stack lifetime beyond 10 years. |
| RF Transceiver Battery Backup | Industrial PLC Real-Time Clock Hold-Up |
Use Scenario: Preserving configuration and calibration data in cellular base station transceivers during battery replacement. IC Role / Device Role / Timing Role: Regulates 2.5V VSYS from Li-ion battery (VCAP) during normal operation, then reverses to backup mode when battery is disconnected. Use Value: 40μA Burst Mode IQ minimizes battery drain during idle periods; DIR-controlled mode transition avoids software intervention. | Use Scenario: Powering RTC and SRAM in programmable logic controllers during factory power outages lasting seconds to minutes. IC Role / Device Role / Timing Role: Charges low-leakage supercapacitor from 24V industrial bus (via isolated DC/DC), then regulates 3.3V VSYS with <1μA shutdown current. Use Value: Shutdown current ≤1μA enables >1-year backup from 0.47F capacitor; CAPOK signal triggers firmware save before power collapse. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bidirectional buck-boost regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MAX17599ATJ+T | Single-direction (buck-only) with external MOSFETs; no integrated balancer or DIR-controlled switchover | Requires external charger IC and balancing circuit for supercapacitor backup; lacks autonomous mode transition | Select only if cost sensitivity outweighs integration benefits and system can tolerate added BOM complexity |
| TPS63802DLAR | Unidirectional buck-boost (VSYS→VCAP only); no backup mode; 2.5A max but no VCAP supervision or VMID | Suitable for energy harvesting charging only; cannot provide system backup power from VCAP | Choose only for charging-only use cases where bidirectional functionality is unnecessary |
Compared with MAX17599ATJ+T and TPS63802DLAR, the LTC3110IFE#PBF uniquely integrates bidirectional power flow, autonomous switchover, active capacitor balancing, and comprehensive status signaling in a single TSSOP-24 package-reducing total solution size by >40% and eliminating six external components required by alternatives.
Availability
LTC3110IFE#PBF is available at Aetrix Electronics and suitable for server backup power, RAID system hold-up, RF transceiver battery backup, and industrial PLC real-time clock applications requiring stable component supply and guaranteed long-term availability.
Supply support for LTC3110IFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and power management markets.
The LTC3110 product line was designed specifically for high-reliability, long-life supercapacitor and battery backup systems requiring seamless bidirectional energy transfer, autonomous failover, and integrated cell balancing-targeting data center, telecom, and industrial control applications.
FAQ
What is the maximum continuous current capability of the LTC3110IFE#PBF in backup mode?
The LTC3110IFE#PBF supports up to 2A continuous bidirectional current in both charge and backup modes. Its internal MOSFETs (SW1/SW2) feature typical RDS(ON) values of 49–86mΩ, enabling this current level while maintaining thermal stability in the TSSOP-24 package at 125°C ambient. Peak current limit is 6A, but sustained operation is rated at 2A per datasheet specifications under recommended layout and thermal conditions.
How does the LTC3110IFE#PBF handle supercapacitor voltage balancing during charging?
The LTC3110IFE#PBF uses its dedicated VMID pin to actively balance series-connected supercapacitors. The internal linear buffer regulates VMID to exactly half of VCAP, delivering up to ±150mA balancing current. If capacitor mismatch causes VMID deviation beyond the suspend threshold (2.38V–2.62V at VCAP = 5V), charging pauses until balance is restored-preventing overvoltage damage without external circuitry.
Can the LTC3110IFE#PBF operate with VCAP lower than 1.0V during backup mode startup?
Yes, the LTC3110IFE#PBF supports VCAP as low as 0.1V in backup mode, enabling operation even after deep discharge. Startup occurs when VSYS rises above 1.71V (UVLO threshold) and RUN is asserted; the device begins boosting from VCAP ≥ 0.1V to regulate VSYS. This ultra-low start-up voltage extends usable backup time from large supercapacitor banks beyond conventional solutions limited to ≥1.8V.
What is the function of the PROG pin on the LTC3110IFE#PBF and how is it configured?
The PROG pin on the LTC3110IFE#PBF programs the average charge current (IVSYS) drawn from the system rail during charging. A resistor (RPROG) from PROG to SGND sets current via IVSYS = 0.6V / RPROG × 200µA/A. For example, 3.01kΩ yields 2A. RPROG values from 1.5kΩ to 24.3kΩ support 125mA–2A with ±2% accuracy, and the LTC3110IFE#PBF includes thermal foldback above 125°C to protect the system.
Does the LTC3110IFE#PBF require external components for basic operation, and what are the minimum required?
Yes, the LTC3110IFE#PBF requires external components for safe and functional operation. Minimum required parts include: a 2.2µH power inductor between SW1 and SW2; input/output ceramic capacitors (47µF at VSYS, 1µF at VCAP); RPROG resistor for charge current setting; feedback resistors for FB (VSYS regulation) and FBVCAP (end-of-charge voltage); and a 1nF capacitor from VMID to PGND if unused. All are specified in the datasheet's Typical Applications section.
LTC3110IFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Battery Chemistry:
- Supercapacitor
- Number of Cells:
- -
- Current - Charging:
- -
- Programmable Features:
- -
- Fault Protection:
- Over Temperature, Over Voltage
- Charge Current - Max:
- -
- Battery Pack Voltage:
- -
- Voltage - Supply (Max):
- 5.5V
- Interface:
- -
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
LTC3110IFE#PBF FAQ
1.How can I place an order for LTC3110IFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3110IFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3110IFE#PBF reliable?
The price and inventory of LTC3110IFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3110IFE#PBF is usually 5 days.
3.What payment methods are accepted for LTC3110IFE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3110IFE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3110IFE#PBF?
LTC3110IFE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3110IFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3110IFE#PBF?
For technical support, including LTC3110IFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3110IFE#PBF requirements.
6.How does Aetrix verify that LTC3110IFE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3110IFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3110IFE#PBF meets industry standards.
7.What is the process for return or replacement of LTC3110IFE#PBF?
All LTC3110IFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3110IFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3110IFE#PBF part is unused and in its original packaging.
Return procedure for LTC3110IFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3110IFE#PBF Tags
-
BQ21040DBVR
Texas Instruments
-
MCP73812T-420I/OT
Microchip Technology
-
MCP73831T-2ACI/OT
Microchip Technology
-
MCP73832T-2ACI/OT
Microchip Technology
-
MCP73831T-2DCI/OT
Microchip Technology
-
MCP73832T-2DCI/OT
Microchip Technology
-
MCP73831T-2ATI/OT
Microchip Technology
-
MCP73832T-2ATI/OT
Microchip Technology
-
MCP73831T-5ACI/OT
Microchip Technology
-
MCP73832T-2ACI/MC
Microchip Technology
-
MCP73831T-2ACI/MC
Microchip Technology
-
MCP73831T-2ATI/MC
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
