Analog Devices Inc. LTC3122IDE#PBF
- Part No.:
- LTC3122IDE#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 12-WFDFN Exposed Pad
- Datasheet:
-
LTC3122IDE#PBF.pdf
- Description:
- IC REG BOOST ADJ 2.5A 12DFN
- Quantity:
- Payment:

- Shipping:

Inventory:614
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Product details
Overview
LTC3122IDE#PBF from Analog Devices (formerly Linear Technology) is a synchronous step-up DC/DC converter with true output disconnect, 2.5A current limit, adjustable 100kHz–3MHz switching frequency, and operation down to 500mV input after startup. It delivers up to 15V output from low-voltage sources such as single-cell Li-ion or backup capacitors, enabling high-efficiency power for RF power stages and piezo actuators.
For engineers reviewing the LTC3122IDE#PBF datasheet, LTC3122IDE#PBF pinout, LTC3122IDE#PBF application, or LTC3122IDE#PBF equivalent, key selection criteria include its 2.5A peak switch current, <1µA shutdown current, Burst Mode® quiescent current of 25µA, output disconnect capability, and support for external clock synchronization in noise-sensitive systems.
Technical Context
The LTC3122IDE#PBF employs current-mode PWM control with adaptive slope compensation for stable regulation across wide VIN/VOUT ratios and fast transient response. Its dual-MOSFET synchronous rectification-using an N-channel main switch (RDS(ON) = 0.121Ω) and P-channel rectifier (RDS(ON) = 0.188Ω)-enables up to 95% efficiency while eliminating body-diode conduction during shutdown.
It integrates a 10ms closed-loop soft-start, zero-current detection for light-load efficiency, anti-ringing control above VIN+2V, and overvoltage lockout at ~16.2V. The VCC regulator autonomously selects between VIN and VOUT to maintain 4.25V internal bias, supporting operation even when VIN drops below 3V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 1.8V to 5.5V start-up; sustains regulation down to 0.5V after VOUT ≥ 2.2V - enables deep discharge of battery or capacitor sources |
| Output Voltage Range | 2.2V to 15V programmable via FB resistor divider - supports 12V analog rails and high-voltage piezo drivers |
| Switch Current Limit | 2.5A typical (3.5A max), independent of VIN/VOUT - ensures robust load handling without external sensing |
| Quiescent Current | 25µA in Burst Mode®, <1µA in shutdown - extends battery life in always-on sensor nodes |
| Switching Frequency | Adjustable 0.1–3MHz via RT resistor or external SYNC clock - balances efficiency vs. size in space-constrained designs |
| Efficiency | Up to 95% with synchronous rectification - eliminates Schottky losses and reduces thermal load |
| Output Disconnect | True disconnect in shutdown: VOUT fully discharges, no reverse current - prevents backfeed and enables safe hot-swap |
Pinout & Package
Package: 12-lead (4mm × 3mm × 0.75mm) plastic DFN with exposed PGND pad (Pin 13), rated for –40°C to 125°C junction temperature. Exposed pad must be soldered to PCB ground plane for θJA = 43°C/W thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW (1) | Switch node | Connects to inductor; internal anti-ringing resistor activates when VOUT ≥ VIN + 2V to suppress EMI |
| PGND (2,13) | Power ground | Low-impedance return for high-current paths; exposed pad is PGND and mandatory for thermal performance |
| VIN (3) | Main input supply | Powers device unless VOUT > VIN and VIN < 3V; requires ≥4.7µF ceramic bypass to PGND |
| PWM/SYNC (4) | Mode control & sync input | High = fixed-frequency PWM; Low = Burst Mode®; external clock = synchronized operation (100ns–2µs pulse width) |
| VCC (5) | Internal LDO output | Regulated ~4.25V rail derived from VIN or VOUT; powers gate drivers and control logic; requires ≥4.7µF capacitor |
| RT (6) | Oscillator programming | Resistor to SGND sets fOSC = 57.6/RT (MHz); for SYNC, set RT = 73.2/fSYNC (kΩ) ≈ 25% below target frequency |
| VC (7) | Error amplifier output | Compensation node for loop stability; connects RC network to SGND per operating conditions |
| FB (8) | Feedback input | Senses resistive divider; regulates VOUT = 1.202V × (1 + R1/R2); input bias current ≤50nA |
| SD (9) | Shutdown control | Logic-level enable: >1.6V = active, <0.25V = shutdown with <1µA IQ; tolerant of voltages above VIN/VOUT |
| SGND (10) | Signal ground | Reference for FB, VC, and CAP; must tie directly to (–) side of output capacitor, separate from PGND at single point |
| VOUT (11) | Regulated output & rectifier source | Drives synchronous P-MOSFET gate; disconnected from VIN during SD = low; requires ≥10µF ceramic to PGND |
| CAP (12) | Synchronous rectifier reference | Capacitor to VOUT creates ~5.6V below VOUT rail to drive P-MOSFET gate; typically 100nF ceramic |
Key Features
| Feature | Design Value |
|---|---|
| True output disconnect | Eliminates reverse current and enables full VOUT discharge in shutdown - critical for system-level power sequencing and safety |
| Programmable 100kHz–3MHz switching | Optimizes trade-off between inductor size (high f) and conduction loss (low f) without changing layout |
| Burst Mode® operation | Reduces IQ to 25µA at light loads while maintaining regulation - extends runtime in battery-powered IoT endpoints |
| Inrush current limiting | 10ms closed-loop soft-start prevents input surge during turn-on - protects weak sources like supercapacitors |
| Robust protection suite | Includes short-circuit current foldback (1.6A limit), thermal shutdown (170°C), output overvoltage lockout (16.2V), and UVLO on VCC |
Applications
| RF Power Amplifier Bias | Piezo Actuator Driver |
|---|---|
Use Scenario: Generating stable 12V bias for GaAs FET amplifiers in portable radios or IoT transceivers powered by single-cell Li-ion. IC Role / Device Role / Timing Role: Synchronous boost converter providing regulated, low-noise 12V rail with output disconnect to prevent RF stage latch-up during sleep. Use Value: Enables >95% efficiency at 800mA load and <1µA shutdown current - maximizes transmit time per charge cycle. |
Use Scenario: Driving high-voltage piezoelectric elements (e.g., ultrasonic cleaners, precision positioning stages) requiring 5–15V with fast transient response. IC Role / Device Role / Timing Role: Adjustable-output boost converter delivering precise voltage with zero-current detection to minimize idle power. Use Value: Programmable 2.2–15V range and 3.5A peak current support rapid actuator charging without external MOSFETs. |
| Small DC Motor Supply | 12V Analog Rail Generator |
Use Scenario: Powering miniature brushed DC motors (e.g., in medical pumps or robotics) from 3.3V or 5V logic rails with controlled start-up torque. IC Role / Device Role / Timing Role: Step-up converter with inrush limiting and soft-start to avoid motor stall current spikes during activation. Use Value: 2.5A current limit and 10ms soft-start ensure reliable motor spin-up without brownout on shared supply rails. |
Use Scenario: Creating isolated 12V analog supply for op-amps, ADCs, or DACs in mixed-signal systems using 5V or backup capacitor sources. IC Role / Device Role / Timing Role: High-PSRR, low-noise boost converter with output disconnect to prevent analog section contamination during digital sleep modes. Use Value: <1µA shutdown IQ and true disconnect preserve analog rail integrity and eliminate leakage paths to digital domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous boost converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS61088RHLR | Higher 5.5A switch current, fixed 500kHz/1MHz/2.2MHz options, no external SYNC, no true output disconnect | Lacks output disconnect and external clock sync - unsuitable for systems requiring VOUT discharge or EMI-controlled timing | Select when higher peak current is needed and output disconnect is not required; verify layout for 5.5A switching. |
| MAX17222ETA+ | Lower 1.2A current limit, 1.2MHz fixed frequency, 0.7V start-up, no programmable fOSC or SYNC, no output disconnect | Optimized for ultra-low-VIN coin-cell apps; lacks flexibility for 12V+ outputs and noise-sensitive sync requirements | Prefer for sub-1A, sub-5V output designs where minimal footprint and lowest start-up voltage are primary concerns. |
Compared with TPS61088RHLR and MAX17222ETA+, the LTC3122IDE#PBF uniquely combines true output disconnect, 100kHz–3MHz programmability with SYNC, and 2.5A current capability in a thermally enhanced DFN - making it optimal for noise-sensitive, battery-extending, and system-safe boost applications where VOUT control and sequencing matter.
Availability
LTC3122IDE#PBF is available at Aetrix Electronics and suitable for RF power amplifiers, piezo actuator drivers, small DC motor supplies, and 12V analog rail generation requiring stable component supply across industrial, medical, and portable electronics programs.
Supply support for LTC3122IDE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its legacy of high-performance power management ICs with rigorous characterization and long-term product support.
The LTC3122IDE#PBF belongs to Linear's high-efficiency synchronous boost converter family, designed specifically for applications demanding wide input range, true output disconnect, and flexible frequency control in space- and power-constrained systems.
FAQ
What is the minimum input voltage required for the LTC3122IDE#PBF to start up and regulate?
The LTC3122IDE#PBF requires a minimum start-up voltage of 1.8V to initiate regulation. Once VOUT reaches ≥2.2V, it continues regulating even as VIN falls to 0.5V - a key feature for maximizing energy extraction from depleting batteries or backup capacitors. This behavior is confirmed in the Electrical Characteristics table under "Minimum Start-Up Voltage" and "Input Voltage Range After VOUT ≥ 2.2V".
Does the LTC3122IDE#PBF provide true output disconnect, and how is it implemented?
Yes, the LTC3122IDE#PBF provides true output disconnect during shutdown: when SD is pulled low, the internal P-channel synchronous rectifier is fully turned off, preventing body-diode conduction and allowing VOUT to discharge completely to 0V. This eliminates reverse current flow and is explicitly documented in the Features list, Applications section, and Pin Functions description for Pin 11 (VOUT).
How does Burst Mode® operation reduce quiescent current in the LTC3122IDE#PBF?
In Burst Mode®, the LTC3122IDE#PBF delivers energy in discrete bursts until VOUT reaches regulation, then enters sleep mode drawing only 25µA from VIN. When VOUT droops ~1%, switching resumes. This is enabled by pulling PWM/SYNC low and is validated in the Electrical Characteristics table (25µA Burst Mode IQ) and Applications Information section.
Can the LTC3122IDE#PBF be synchronized to an external clock, and what are the requirements?
Yes, the LTC3122IDE#PBF can synchronize its oscillator to an external clock applied to the PWM/SYNC pin. The external signal must have 100ns–2µs pulse width, and RT must be set to 73.2/fSYNC (kΩ) - approximately 25% below the target sync frequency. This capability is detailed in the Pin Functions description for PWM/SYNC and the Oscillator section of the Applications Information.
What thermal considerations apply to the LTC3122IDE#PBF's DFN package?
The LTC3122IDE#PBF in the 12-lead DFN package requires the exposed PGND pad (Pin 13) to be soldered to the PCB ground plane to achieve the specified θJA = 43°C/W. Failure to do so results in significantly higher thermal impedance and potential thermal shutdown. This requirement is stated in both the Absolute Maximum Ratings footnote and the Package Description diagram.
LTC3122IDE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 12-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Up
- Output Configuration:
- Positive
- Topology:
- Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 1.8V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 2.2V
- Voltage - Output (Max):
- 15V
- Current - Output:
- 2.5A (Switch)
- Frequency - Switching:
- 1MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-DFN (4x3)
LTC3122IDE#PBF FAQ
1.How can I place an order for LTC3122IDE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3122IDE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3122IDE#PBF reliable?
The price and inventory of LTC3122IDE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3122IDE#PBF is usually 5 days.
3.What payment methods are accepted for LTC3122IDE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3122IDE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3122IDE#PBF?
LTC3122IDE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3122IDE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3122IDE#PBF?
For technical support, including LTC3122IDE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3122IDE#PBF requirements.
6.How does Aetrix verify that LTC3122IDE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3122IDE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3122IDE#PBF meets industry standards.
7.What is the process for return or replacement of LTC3122IDE#PBF?
All LTC3122IDE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3122IDE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3122IDE#PBF part is unused and in its original packaging.
Return procedure for LTC3122IDE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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