Analog Devices Inc. LTC3124IDHC#PBF

Overview

LTC3124IDHC#PBF from Analog Devices (formerly Linear Technology) is a dual-phase, synchronous step-up DC/DC converter with true output disconnect and inrush current limiting, delivering up to 15V output from inputs as low as 1.8V start-up or 500mV post-start. It features programmable switching frequency (100kHz–3MHz), 2.5A per-phase current limit, and Burst Mode operation achieving 25µA quiescent current-enabling high-efficiency power conversion for RF power amplifiers, piezo actuators, and 12V analog rails from single-cell batteries.

For engineers reviewing the LTC3124IDHC#PBF datasheet, LTC3124IDHC#PBF pinout, LTC3124IDHC#PBF application, or LTC3124IDHC#PBF equivalent, key selection criteria include dual-phase ripple reduction, sub-1µA shutdown current, output disconnect capability, adjustable 2.5V–15V output, and thermal-enhanced 3mm × 5mm DFN packaging with exposed PGND pad.

Technical Context

The LTC3124IDHC#PBF implements current-mode PWM control with adaptive slope compensation, enabling fast load transient response and stable regulation across wide input/output ranges. Its dual-phase architecture operates SWA and SWB 180° out-of-phase, reducing output capacitor ripple current by ~70% versus single-phase equivalents while maintaining 94% maximum duty cycle and internal soft-start ramping over 10ms.

It integrates N-channel MOSFET switches (0.13Ω R_DS(ON)) and P-channel synchronous rectifiers, supported by lossless peak-current sensing, zero-current detection (~50mA threshold), and anti-ringing circuitry activated when V_OUT ≥ V_IN + 2V. The VC pin hosts a Type III compensation network, and CAP pin establishes a V_OUT–5.4V bias rail for synchronous gate drive.

Key Specifications

Pinout & Package

Package: 16-lead (5mm × 3mm × 0.75mm) plastic DFN with exposed thermal pad (Pin 17 = PGND). Requires soldering of exposed pad to PCB ground plane for rated θ_JA = 43°C/W and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous boost converter applications.

Compared with LT3467EDD#PBF and TPS61088RHLR, the LTC3124IDHC#PBF uniquely combines dual-phase ripple suppression, true output disconnect, 500mV operational capability, and 25µA Burst Mode - making it optimal for battery-constrained, noise-sensitive, and high-reliability analog/RF systems.

Availability

LTC3124IDHC#PBF is available at Aetrix Electronics and suitable for RF power amplifier biasing, piezo actuator drive, and 12V analog rail generation requiring stable component supply, long-lifecycle assurance, and industrial-grade temperature performance.

Supply support for LTC3124IDHC#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its high-performance power management portfolio with rigorous qualification and long-term product support.

The LTC3124 belongs to Linear's precision synchronous boost converter family, designed specifically for demanding analog, RF, and portable industrial applications requiring ultra-low quiescent current, wide input range, and robust fault protection.

FAQ

What is the minimum input voltage required to start up the LTC3124IDHC#PBF?

The LTC3124IDHC#PBF starts up from a minimum input voltage of 1.8V. Once started, it continues regulating output voltages ≥2.5V even as input drops to 500mV - a critical feature for maximizing energy extraction from deeply discharged batteries or backup capacitors. This behavior is confirmed in the Electrical Characteristics table under "Minimum Start-Up Voltage" and "Input Voltage Range".

Does the LTC3124IDHC#PBF provide true output disconnect, and how is it implemented?

Yes, the LTC3124IDHC#PBF provides true output disconnect: when the SD pin is pulled low (<0.25V), both internal P-channel synchronous rectifiers turn off, physically isolating VOUTA/VOUTB from VIN. This prevents backfeed and eliminates standby current leakage - verified in the Functional Description and Absolute Maximum Ratings sections, where VOUT pins tolerate –0.3V and remain floating during shutdown.

How is switching frequency programmed on the LTC3124IDHC#PBF, and what is the relationship between RT and f_SW?

Switching frequency is set via an external resistor (RT) from Pin 8 (RT) to SGND. The per-phase switching frequency follows f_SW ≈ 28 / R_T(kΩ) MHz - e.g., 28kΩ yields 1MHz. The oscillator runs at 2× f_SW, so RT sets f_OSC ≈ 56 / R_T(kΩ) MHz. This formula is explicitly given in the Operation section and validated in Table 1 of the datasheet.

What protection features does the LTC3124IDHC#PBF include, and how are they triggered?

The LTC3124IDHC#PBF includes overvoltage lockout (16.5V on VOUT), thermal shutdown (170°C typical), and short-circuit current limiting (2.5A/phase peak). Output overvoltage halts switching immediately; thermal shutdown disables all FETs until die cools by ~7°C; current limit acts per-phase via peak-detection comparators. All are documented in the Absolute Maximum Ratings and Operation sections with test conditions.

Can the LTC3124IDHC#PBF operate with input voltages below 1V, and what design considerations apply?

Yes - the LTC3124IDHC#PBF sustains regulation with inputs as low as 500mV after start-up (for VOUT ≥ 2.5V). However, at such low VIN, PCB trace resistance and inductor DCR become dominant loss factors, and maximum duty cycle is clamped at 94%. Designers must minimize parasitic resistance and verify power delivery capability using the efficiency curves in Figure G01–G03.