Analog Devices Inc. LTC3265EDHC#PBF

Overview

LTC3265EDHC#PBF from Analog Devices (formerly Linear Technology) is a low-noise dual-polarity power supply IC integrating a boost charge pump, inverting charge pump, and two post-regulating LDOs - delivering ±15V outputs from a single 12V input. It supports up to 50mA per LDO, operates with 135µA quiescent current in Burst Mode®, and uses ceramic capacitors exclusively. It serves as a compact bipolar bias generator for precision analog signal chains.

For engineers reviewing the LTC3265EDHC#PBF datasheet, LTC3265EDHC#PBF pinout, LTC3265EDHC#PBF application, or LTC3265EDHC#PBF equivalent, key selection criteria include dual LDO noise performance (100µVRMS), programmable 50–500kHz oscillator frequency via RT pin, ±4.5V to ±32V input flexibility, Burst Mode vs constant-frequency trade-offs, and DFN-18 thermal design requirements.

Technical Context

The LTC3265EDHC#PBF implements a two-stage architecture: first, charge pumps generate intermediate rails (VOUT+ = 2•VIN_P or 0.94•2•VIN_P; VOUT– = –VIN_N or –0.94•VIN_N), then independent positive/negative LDOs regulate those rails with adjustable output voltages. Each LDO features dedicated ADJ and BYP pins enabling precise feedback control and 100µVRMS noise reduction via external 100nF bypass caps.

Its MODE pin selects between Burst Mode® (135µA IQ, hysteretic regulation, higher ripple) and constant-frequency operation (50–500kHz, fixed 500kHz when RT = GND), while EN+ and EN– independently enable boost/LDO+ and inverting/LDO– sections. Thermal protection disables outputs above ~175°C, and short-circuit limits are 220mA (VOUT+) and 160mA (VOUT–).

Key Specifications

Pinout & Package

Package: 18-lead (5mm × 3mm × 0.75mm) plastic DFN with exposed thermal pad (Pin 19 = GND). Requires soldering of exposed pad to PCB ground plane for thermal compliance (θJA = 42°C/W) and functional integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-polarity regulator applications.

Compared with MAX1044CSA+ and LT3467EFE#PBF, the LTC3265EDHC#PBF uniquely integrates dual charge pumps *and* dual LDOs in one DFN package, delivers 50mA per rail with 100µVRMS noise, and supports programmable frequency and Burst Mode - making it the only option for compact, low-noise, battery-aware bipolar supply designs.

Availability

LTC3265EDHC#PBF is available at Aetrix Electronics and suitable for industrial process transmitters, portable medical diagnostics, and high-resolution test equipment requiring stable component supply across extended temperature ranges (–40°C to 125°C).

Supply support for LTC3265EDHC#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains its legacy of high-performance analog ICs, particularly in power management and precision signal conditioning.

The LTC3265EDHC#PBF belongs to Linear's low-noise power management portfolio, designed specifically for applications demanding clean, bipolar supplies - such as precision data converters, medical sensors, and instrumentation front-ends.

FAQ

What is the maximum allowable input voltage on the VIN_N pin of the LTC3265EDHC#PBF?

The absolute maximum rating for VIN_N is 36V, but the specified operating range is 4.5V to 32V. Exceeding 32V may cause parametric degradation or premature failure, even if within absolute max limits. The LTC3265EDHC#PBF achieves optimal regulation and efficiency when VIN_N is within this 4.5–32V window - for example, using a 24V industrial bus to generate –24V intermediate rail before LDO– regulation.

Can the LTC3265EDHC#PBF generate symmetric ±15V outputs from a 12V input?

Yes - configure VIN_N tied to VOUT+ (not VIN_P), so the inverting pump generates –VOUT+ ≈ –24V, then set LDO– to –15V using its ADJ– resistor divider. Simultaneously set LDO+ to +15V. This yields matched ±15V rails with common-mode rejection benefits. The LTC3265EDHC#PBF datasheet Figure TA01a demonstrates this exact configuration with 12V input and ±15V outputs.

How does Burst Mode® operation affect output ripple on the LTC3265EDHC#PBF?

Burst Mode® increases peak-to-peak output ripple on VOUT+ and VOUT– compared to constant-frequency mode - typically 2–3× higher - due to hysteretic regulation and intermittent switching. However, LDO+ and LDO– post-regulation suppress this ripple to 100µVRMS (with BYP+/- caps). The LTC3265EDHC#PBF remains suitable for noise-sensitive loads because the LDOs provide >60dB PSRR above 10kHz.

Is an external capacitor required on the BYP+ and BYP– pins of the LTC3265EDHC#PBF?

A 100nF ceramic capacitor from BYP+ to GND (and similarly BYP– to GND) is optional but strongly recommended to achieve the specified 100µVRMS LDO output noise. Without these caps, LDO noise rises significantly - measured at >300µVRMS in typical conditions. The LTC3265EDHC#PBF's internal 1.2V reference is bypassed by these caps, directly improving regulation fidelity.

What thermal considerations apply to the LTC3265EDHC#PBF in its DFN-18 package?

The LTC3265EDHC#PBF's DFN-18 package has θJA = 42°C/W and requires soldering of the exposed thermal pad (Pin 19) to a minimum 200mm² PCB copper area for rated performance. At 100mW dissipation, junction temperature rise is ~4.2°C above ambient - but full 50mA load on both LDOs can exceed 250mW. Thermal shutdown activates at ~175°C, so board-level thermal design is critical for continuous operation in enclosed environments.