Analog Devices Inc. LTC3265EFE#PBF
- Part No.:
- LTC3265EFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC3265EFE#PBF.pdf
- Description:
- IC REG CHARG PUMP INV DL 20TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:205
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Product details
Overview
LTC3265EFE#PBF from Analog Devices (formerly Linear Technology) is a low-noise dual-polarity power supply IC integrating a boost charge pump, inverting charge pump, and two post-regulating LDOs - delivering ±15V outputs from a single 12V input. It supports up to 50mA per LDO, operates with ceramic capacitors only, and features programmable 50kHz–500kHz switching frequency and 135µA quiescent current in Burst Mode® with both LDOs active.
For engineers reviewing the LTC3265EFE#PBF datasheet, LTC3265EFE#PBF pinout, LTC3265EFE#PBF application, or LTC3265EFE#PBF equivalent, key selection considerations include bipolar output noise performance (100µVRMS), independent enable/control of positive/negative paths, VINP (4.5–16V) and VINN (4.5–32V) voltage range flexibility, and thermal-enhanced 20-lead TSSOP packaging for industrial instrumentation biasing.
Technical Context
The LTC3265EFE#PBF implements two independent charge pump topologies: a boost converter generating VOUT+ = 2·VINP (constant frequency) or 0.94·2·VINP (Burst Mode), and an inverting converter generating VOUT– = –VINN or –0.94·VINN. Each feeds a dedicated low-noise LDO - LDO+ regulated by ADJ+ reference (1.200V typ), LDO– by ADJ– (–1.200V typ) - enabling precise ±1.2V to ±32V adjustable outputs.
Operation is controlled via three logic inputs: EN+ enables boost/LDO+, EN– enables inverter/LDO–, and MODE selects between constant-frequency (50–500kHz, RT-programmable) and Burst Mode (135µA IQ, hysteretic regulation). The 20-lead TSSOP package includes exposed thermal pad (Pin 21 = GND) with θJA = 38°C/W.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VINP Range | 4.5V to 16V - powers boost pump and LDO+; supports common industrial rails including 5V, 12V, and 15V inputs. |
| VINN Range | 4.5V to 32V - powers inverting pump and LDO–; enables asymmetric negative bias generation up to –32V. |
| LDO Output Current | ±50mA max - sufficient for op-amp biasing, ADC/DAC reference supplies, and sensor excitation circuits. |
| Quiescent Current (Burst) | 135µA with both LDOs on - enables ultra-low-power operation in battery-backed or always-on instrumentation. |
| Output Noise | 100µVRMS (with 100nF BYP+/- caps) - meets stringent requirements for precision analog signal chains and low-phase-noise clocking. |
| Oscillator Frequency | 50kHz to 500kHz (RT-programmable) - allows trade-off between efficiency, EMI, and capacitor size in layout-constrained designs. |
| Dropout Voltage | 400mV (LDO+), 200mV (LDO–) at full load - ensures stable regulation even under high-current, low-headroom conditions. |
Pinout & Package
The LTC3265EFE#PBF is housed in a thermally enhanced 20-lead plastic TSSOP package (JEDEC MO-153) with exposed GND pad (Pin 21). Package dimensions: 6.5mm × 4.4mm × 1.1mm. Thermal resistance θJA = 38°C/W with standard 2-layer PCB and 1-in² copper pour.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 11 | NC | No-connect pins - electrically isolated from die; may be left floating or tied to GND for mechanical stability. |
| 2 | CBST– | Boost charge pump flying capacitor negative terminal - requires low-ESR ceramic cap (1µF typical) between CBST– and CBST+. |
| 3 | CBST+ | Boost charge pump flying capacitor positive terminal - forms switched-capacitor doubler with CBST–. |
| 4 | VIN_P | Main input for boost pump - must be bypassed with ≥10µF ceramic capacitor; 4.5–16V operating range. |
| 5 | EN– | Enable input for inverting pump and LDO– - logic high (≥1.1V) activates path; internal 0.7µA pull-down prevents floating. |
| 6 | BYP– | LDO– reference bypass - connect 100nF capacitor to GND to reduce output noise; leave open if unused. |
| 7 | ADJ– | Negative LDO feedback node - regulates LDO– to –1.200V reference; sets output via resistor divider to GND. |
| 8 | LDO– | Negative LDO output - delivers up to –50mA; requires ≥2µF low-ESR ceramic capacitor to GND for stability. |
| 9 | VOUT– | Inverting charge pump output - provides –VINN (constant freq) or –0.94·VINN (Burst Mode) to LDO– input. |
| 10 | CINV– | Inverting pump flying capacitor positive terminal - forms switched-capacitor inverter with CINV+. |
| 12 | RT | Oscillator frequency programming - resistor to GND sets 50–500kHz; 0Ω → 500kHz default. |
| 13 | EN+ | Enable input for boost pump and LDO+ - logic high (≥1.1V) activates path; internal 0.7µA pull-down. |
| 14 | MODE | Operating mode select - high = Burst Mode (low IQ), low = constant frequency; determines regulation method for both pumps. |
| 15 | BYP+ | LDO+ reference bypass - connect 100nF capacitor to GND to reduce output noise; leave open if unused. |
| 16 | ADJ+ | Positive LDO feedback node - regulates LDO+ to +1.200V reference; sets output via resistor divider to GND. |
| 17 | LDO+ | Positive LDO output - delivers up to +50mA; requires ≥2µF low-ESR ceramic capacitor to GND for stability. |
| 18 | VOUT+ | Boost charge pump output - provides 2·VINP (constant freq) or 0.94·2·VINP (Burst Mode) to LDO+ input. |
| 19 | CINV+ | Inverting pump flying capacitor negative terminal - forms switched-capacitor inverter with CINV–. |
| 20 | VIN_N | Input for inverting pump - tied to VINP for asymmetric outputs (e.g., +15V/–12V) or VOUT+ for symmetric (e.g., ±15V). |
| 21 | GND | Ground reference and thermal pad - exposed pad must be soldered to PCB ground plane for electrical integrity and thermal performance. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enable control | Separate EN+ and EN– pins allow selective activation of positive/negative rails - critical for power sequencing in mixed-signal systems. |
| Ultra-low-noise LDO post-regulation | 100µVRMS output noise with optional BYP+/BYP– caps - enables clean biasing for high-resolution SAR ADCs and low-noise op-amps. |
| Programmable switching frequency | 50kHz–500kHz via RT-to-GND resistor - permits EMI optimization and capacitor size reduction without changing layout. |
| Burst Mode® with 135µA IQ | 135µA total quiescent current with both LDOs enabled - extends battery life in portable test equipment and remote sensors. |
| Robust protection suite | Integrated short-circuit (220mA/160mA) and thermal shutdown (175°C trip) - eliminates need for external fault management circuitry. |
| Ceramic-capacitor-only design | Stable with ≥2µF X7R/X5R ceramics on LDO outputs - reduces board area, cost, and aging concerns vs. tantalum/electrolytic solutions. |
Applications
| High-Precision Instrumentation Bias | Industrial Data Acquisition Front-End |
|---|---|
|
Use Scenario: Powering dual-supply op-amps and precision ADC drivers in handheld multimeters and portable oscilloscopes. IC Role / Device Role / Timing Role: LTC3265EFE#PBF generates matched ±15V rails from a single 12V Li-ion pack, with <100µVRMS noise ensuring sub-LSB error in 24-bit converters. Use Value: Eliminates discrete DC/DC + linear regulator combos, reducing BOM count by 40% and improving long-term drift stability. |
Use Scenario: Supplying isolated analog front-ends in PLC I/O modules requiring ±12V for signal conditioning and sensor excitation. IC Role / Device Role / Timing Role: LTC3265EFE#PBF delivers regulated ±12V from 24V system rail using VINN tied to VOUT+, enabling symmetric outputs with minimal component count. Use Value: Achieves >75dB PSRR at 100kHz for noise-sensitive transducer interfaces while maintaining 135µA standby current during sleep cycles. |
| Low-Noise Audio Signal Chain | Medical Imaging Sensor Bias |
|
Use Scenario: Providing ultra-clean ±5V supplies for MEMS microphone preamps and Class-AB headphone amplifiers in clinical audio recorders. IC Role / Device Role / Timing Role: LTC3265EFE#PBF uses BYP+/BYP– 100nF caps and Burst Mode to achieve 100µVRMS noise and <150µA IQ - critical for dynamic range preservation. Use Value: Reduces audible hiss by 12dB vs. standard charge-pump ICs, meeting IEC 60601-2-27 EMI immunity requirements. |
Use Scenario: Biasing photodiode arrays and CCD readout circuits in portable ultrasound probes where leakage current and noise directly impact image SNR. IC Role / Device Role / Timing Role: LTC3265EFE#PBF supplies ±3.3V rails with <0.03mV/mA load regulation and 200mV LDO– dropout - enabling stable bias under pulsed imaging loads. Use Value: Enables 16-bit effective resolution in time-of-flight measurements by suppressing supply-induced timing jitter below 1ps RMS. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-polarity power supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT3467EDD#PBF | Single-output boost + inverter (no integrated LDOs); higher 2.5mA IQ; requires external regulators for low-noise outputs. | Suitable for space-constrained designs where post-regulation noise is less critical and external LDOs are acceptable. | Select when board area is primary constraint and system-level noise filtering can be added externally. |
| TPS65131RGTR | Fixed ±15V outputs (no adjustability); 1.2mA IQ; no Burst Mode; smaller 16-pin QFN; lower max VINN (14V). | Applicable in consumer displays and LCD biasing where fixed rails and compact footprint outweigh programmability needs. | Choose for cost-sensitive, high-volume display applications requiring only standard ±15V without adjustment or ultra-low IQ. |
Compared with LT3467EDD#PBF and TPS65131RGTR, the LTC3265EFE#PBF uniquely integrates fully adjustable low-noise LDOs, Burst Mode operation, and wide-input flexibility - making it the only option capable of delivering ±1.2V to ±32V at 50mA with <100µVRMS noise and <150µA quiescent current in a single IC.
Availability
LTC3265EFE#PBF is available at Aetrix Electronics and suitable for high-precision instrumentation biasing, industrial data acquisition front-ends, and medical imaging sensor biasing requiring stable component supply across extended temperature ranges (–40°C to 125°C).
Supply support for LTC3265EFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its legacy of high-performance analog ICs. Linear Technology was founded in 1981 and specialized in precision power management, signal conditioning, and RF solutions.
The LTC3265EFE#PBF belongs to Linear's low-noise power management product line, designed specifically for instrumentation, medical, and test equipment requiring bipolar supplies with ultra-low output noise and flexible sequencing.
FAQ
What is the maximum allowable input voltage on VIN_N for the LTC3265EFE#PBF?
The absolute maximum rating for VIN_N is 36V, but the specified operating range is 4.5V to 32V. Exceeding 32V risks violating guaranteed performance specifications such as regulation accuracy, short-circuit current limit, and thermal behavior. For reliable operation across –40°C to 125°C, VIN_N must remain within 4.5V–32V. The LTC3265EFE#PBF datasheet confirms this range applies to all temperature grades including the E-grade version.
Can the LTC3265EFE#PBF generate symmetric ±15V outputs from a 12V input?
Yes. Tie VIN_N to VOUT+ (not VIN_P), configure MODE = low for constant-frequency operation, set RT = GND for 500kHz, and use resistor dividers to set LDO+ and LDO– to ±15V. With VIN_P = 12V, VOUT+ reaches 24V, so VIN_N = 24V yields VOUT– = –24V, allowing LDO– to regulate to –15V. This configuration is explicitly validated in the LTC3265EFE#PBF typical application diagram (TA01a) and achieves <100µVRMS noise on both rails.
Does the LTC3265EFE#PBF require external diodes or MOSFETs for charge pump operation?
No. The LTC3265EFE#PBF integrates all necessary switching elements internally - including four MOSFETs per charge pump stage - eliminating external diodes or FETs. Only external flying capacitors (CBST±, CINV±), input/output bypass capacitors, and feedback resistors are required. This is confirmed in the block diagram and pin functions section of the LTC3265EFE#PBF datasheet, which shows no external switch connections.
How does Burst Mode® operation affect output voltage ripple on the LTC3265EFE#PBF?
Burst Mode® increases peak-to-peak output ripple compared to constant-frequency mode due to hysteretic regulation and intermittent switching. Typical VOUT+ ripple rises from ~20mVP-P (constant freq) to ~80mVP-P (Burst Mode), but LDO post-regulation suppresses this to <100µVRMS on LDO+ and LDO– outputs. The LTC3265EFE#PBF datasheet specifies that Burst Mode is intended for light-load conditions where IQ reduction outweighs ripple concerns.
Is the exposed thermal pad on the LTC3265EFE#PBF package electrically connected?
Yes. Pin 21 (exposed pad) is internally connected to GND and must be soldered to the PCB ground plane. Thermal performance (θJA = 38°C/W) and electrical stability depend on this connection. The LTC3265EFE#PBF datasheet explicitly states "EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB" - failure to do so degrades thermal dissipation and may cause overtemperature shutdown.
LTC3265EFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Ratiometric
- Output Configuration:
- Positive and Negative (Dual Rail)
- Topology:
- Charge Pump
- Output Type:
- Fixed
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 32V
- Voltage - Output (Min/Fixed):
- -Vin, 2Vin
- Voltage - Output (Max):
- -
- Current - Output:
- 100mA
- Frequency - Switching:
- 50kHz ~ 500kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-TSSOP-EP
LTC3265EFE#PBF FAQ
1.How can I place an order for LTC3265EFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3265EFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3265EFE#PBF reliable?
The price and inventory of LTC3265EFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3265EFE#PBF is usually 5 days.
3.What payment methods are accepted for LTC3265EFE#PBF?
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Once your LTC3265EFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3265EFE#PBF?
For technical support, including LTC3265EFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3265EFE#PBF requirements.
6.How does Aetrix verify that LTC3265EFE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3265EFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3265EFE#PBF meets industry standards.
7.What is the process for return or replacement of LTC3265EFE#PBF?
All LTC3265EFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3265EFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3265EFE#PBF part is unused and in its original packaging.
Return procedure for LTC3265EFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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