Analog Devices Inc. LTC3265HDHC#PBF
- Part No.:
- LTC3265HDHC#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 18-WFDFN Exposed Pad
- Datasheet:
-
LTC3265HDHC#PBF.pdf
- Description:
- IC REG CHARGE PUMP INV DL 18DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3265HDHC#PBF from Analog Devices (formerly Linear Technology) is a low-noise dual-polarity power supply IC integrating a boost charge pump, an inverting charge pump, and two post-regulating LDOs - one positive (LDO+) and one negative (LDO–). It delivers up to 50mA per rail, supports input ranges of 4.5V–16V (VIN_P) and 4.5V–32V (VIN_N), operates with 135µA quiescent current in Burst Mode®, and is rated for –40°C to +150°C junction temperature. It enables precision bipolar bias generation in instrumentation front-ends.
For engineers reviewing the LTC3265HDHC#PBF datasheet, LTC3265HDHC#PBF pinout, LTC3265HDHC#PBF application, or LTC3265HDHC#PBF equivalent, key selection criteria include dual-rail LDO noise performance (100µVRMS), programmable 50kHz–500kHz oscillator frequency via RT pin, ±1.2V reference accuracy over temperature, and thermal protection with 150°C max junction rating.
Technical Context
The LTC3265HDHC#PBF implements a two-stage architecture: first, charge pumps generate intermediate rails (VOUT+ ≈ 2•VIN_P and VOUT– ≈ –VIN_N in constant-frequency mode; or 0.94×2•VIN_P / –0.94•VIN_N in Burst Mode®), then low-noise LDOs regulate those rails to user-programmed outputs. Each LDO uses internal 1.2V (LDO+) or –1.2V (LDO–) references with ±2% accuracy over temperature and load.
Operation is controlled by three logic inputs: EN+ and EN– independently enable the positive and negative paths, while MODE selects between constant-frequency (50–500kHz) and Burst Mode® operation. The RT pin sets oscillator frequency via external resistor, and exposed-pad DFN package provides θJA = 42°C/W for thermal management in high-reliability applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN_P Range | 4.5V to 16V - powers boost charge pump; determines maximum VOUT+ (up to 32V) |
| VIN_N Range | 4.5V to 32V - powers inverting charge pump; determines minimum |VOUT–| (down to –32V) |
| LDO Output Current | ±50mA - sufficient for op-amp biasing, ADC/DAC reference supplies, and sensor excitation |
| Quiescent Current (Burst Mode®) | 135µA with both LDOs active - enables ultra-low-power standby in battery-backed systems |
| Oscillator Frequency Range | 50kHz to 500kHz - adjustable via RT-to-GND resistor; lower frequencies reduce EMI but increase output impedance |
| LDO Output Noise | 100µVRMS (with 100nF BYP+/- caps) - meets low-noise requirements for precision analog signal chains |
| Operating Junction Temp | –40°C to +150°C - qualified for automotive under-hood, industrial control, and downhole instrumentation |
Pinout & Package
Package: 18-lead (5mm × 3mm × 0.75mm) plastic DFN with exposed GND pad (Pin 19), thermally enhanced for high-power-density layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUT+ | Boost charge pump output | Intermediate rail for LDO+; regulated to 2•VIN_P (constant freq.) or 0.94×2•VIN_P (Burst Mode®) |
| LDO+ | Positive LDO output | User-programmable rail (1.2V–32V); requires ≥2µF low-ESR ceramic capacitor for stability |
| ADJ+ | Positive LDO feedback | Servos to 1.200V ±2%; sets output voltage via external resistor divider |
| BYP+ | LDO+ reference bypass | Connect 100nF to GND to reduce output noise; floating if unused |
| MODE | Charge pump operating mode select | High = Burst Mode® (low IQ, higher ripple); Low = constant-frequency (lower ripple, higher IQ) |
| EN+ | Positive path enable | Logic high enables boost pump and LDO+; internal pull-down prevents floating |
| RT | Oscillator frequency programming | 1.2V-regulated input; resistor to GND sets frequency from 50kHz to 500kHz |
| VIN_N | Inverting charge pump input | Accepts 4.5V–32V; tied to VIN_P for asymmetric outputs or VOUT+ for symmetric ± rails |
| CINV+ | Inverting pump flying cap (–) | Connects to negative terminal of flying capacitor; critical for charge transfer efficiency |
| CINV– | Inverting pump flying cap (+) | Connects to positive terminal of flying capacitor; phase-switched with CINV+ |
| LDO– | Negative LDO output | User-programmable rail (–32V to –1.2V); requires ≥2µF low-ESR ceramic capacitor |
| ADJ– | Negative LDO feedback | Servos to –1.200V ±2%; sets negative output voltage via external resistor divider |
| BYP– | LDO– reference bypass | Connect 100nF to GND to reduce negative rail noise; floating if unused |
| VOUT– | Inverting charge pump output | Intermediate rail for LDO–; regulated to –VIN_N (constant freq.) or –0.94•VIN_N (Burst Mode®) |
| GND | Ground reference & thermal pad | Exposed pad (Pin 19) must be soldered to PCB ground plane for electrical integrity and thermal performance |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enable controls (EN+, EN–) | Allows selective activation of positive/negative rails - essential for power sequencing in mixed-signal systems |
| Programmable 50kHz–500kHz oscillator | Enables EMI optimization: lower frequencies reduce radiated emissions; higher frequencies improve transient response and reduce output impedance |
| 100µVRMS LDO output noise (with BYP caps) | Meets stringent noise requirements for high-resolution SAR/Pipeline ADCs and low-noise op-amps |
| Integrated soft-start on all regulators | Prevents inrush current into output capacitors - eliminates supply rail overshoot during power-up |
| Short-circuit and thermal protection | Self-protects against faults: limits VOUT+ to 220mA and VOUT– to 160mA; disables outputs above ~175°C junction temp |
| Stable with ceramic capacitors only | Eliminates need for electrolytic or tantalum output caps - improves reliability and reduces board area |
Applications
| High-Precision Instrumentation Bias | Industrial Data Acquisition Front-End |
|---|---|
Use Scenario: Powering dual-supply op-amps and precision ADC drivers in portable multimeters or handheld analyzers. IC Role / Device Role / Timing Role: Generates matched ±15V low-noise rails from a single 12V battery source; LDO+ and LDO– independently regulate and filter charge pump ripple. Use Value: 100µVRMS noise ensures <18-bit effective resolution in 24-bit sigma-delta ADCs; Burst Mode® extends battery life during idle periods. |
Use Scenario: Supplying isolated analog front-ends in PLC I/O modules requiring wide input voltage tolerance and long-term stability. IC Role / Device Role / Timing Role: Provides ±12V rails from 24V DC bus; VIN_N tied to VIN_P enables asymmetric outputs; thermal rating supports 70°C ambient operation. Use Value: 150°C junction rating and short-circuit protection ensure field reliability; programmable frequency avoids switching harmonics in sensitive measurement bands. |
| Medical Sensor Signal Conditioning | Automotive Radar Bias Supply |
Use Scenario: Biasing low-noise transimpedance amplifiers in optical pulse oximetry sensors. IC Role / Device Role / Timing Role: Delivers ±5V rails with <100µVRMS noise; ADJ+/ADJ– pins set precise reference voltages; BYP+ and BYP– caps suppress broadband noise. Use Value: ±2% reference accuracy over –40°C to +85°C ensures consistent gain calibration across environmental conditions. |
Use Scenario: Generating clean ±10V supplies for RF amplifier biasing in 77GHz radar transceivers mounted near engine compartments. IC Role / Device Role / Timing Role: Operates at –40°C to +150°C junction; exposed-pad DFN dissipates heat efficiently; EN+ and EN– support dynamic rail enable/disable during sleep/wake cycles. Use Value: Thermal shutdown and indefinite short-circuit tolerance prevent failure during ESD events or connector shorts in harsh automotive environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-polarity regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LT3467EDD#PBF | Single-output (positive only) boost + LDO; no inverting pump or negative LDO; 400kHz fixed frequency | Cannot generate negative rails - requires external inverter or second IC for bipolar supplies | Select when only positive bias is needed and space/complexity must be minimized |
| MAX1759EUA+T | Single inverting charge pump + LDO; no boost stage; 500kHz fixed frequency; ±30mA output | Lacks positive rail generation - needs external boost or separate positive supply | Choose for cost-sensitive negative bias only applications where VIN_N ≤ 28V and load ≤ 30mA |
Compared with LT3467EDD#PBF and MAX1759EUA+T, the LTC3265HDHC#PBF uniquely integrates both boost and inverting charge pumps with dual LDOs in one package, enabling true bipolar rail generation without external components - reducing BOM count, layout area, and design validation effort for precision analog systems.
Availability
LTC3265HDHC#PBF is available at Aetrix Electronics and suitable for high-reliability industrial instrumentation, automotive radar subsystems, and medical sensor conditioning requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC3265HDHC#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors.
The LTC3265 belongs to Linear's precision power management product line, designed specifically for low-noise, high-voltage dual-rail generation in test equipment, medical imaging, and industrial process control where signal integrity and thermal robustness are critical.
FAQ
What is the maximum allowable junction temperature for the LTC3265HDHC#PBF?
The LTC3265HDHC#PBF is specified for operation up to +150°C junction temperature, with thermal shutdown activating at approximately +175°C. Its 18-lead DFN package features an exposed GND pad (Pin 19) that must be soldered to the PCB ground plane to achieve the rated θJA of 42°C/W and maintain reliable operation within this range.
How does the MODE pin affect output regulation accuracy and ripple on the LTC3265HDHC#PBF?
When MODE = high, the LTC3265HDHC#PBF enters Burst Mode®: VOUT+ regulates to 0.94×2•VIN_P and VOUT– to –0.94•VIN_N, with higher output ripple but only 135µA quiescent current. When MODE = low, it operates at constant frequency (50–500kHz), delivering exact 2•VIN_P and –VIN_N with lower ripple but higher IQ - ideal for noise-sensitive loads.
Can the LTC3265HDHC#PBF generate symmetric ±15V outputs from a 12V input?
Yes. Tie VIN_N to VOUT+ (not VIN_P), configure MODE = low for constant-frequency operation, and set ADJ+/ADJ– dividers to yield VLDO+ = +15V and VLDO– = –15V. This configuration produces matched rails with typical ripple rejection >60dB - verified in the LTC3265 datasheet Figure TA01b using 12V input and 20mA loads.
What external components are mandatory for stable operation of the LTC3265HDHC#PBF?
Mandatory components include: (1) 10µF ceramic input capacitors on VIN_P and VIN_N; (2) 1µF ceramic flying capacitors on CBST+/CBST– and CINV+/CINV–; (3) ≥2µF low-ESR ceramic capacitors on LDO+ and LDO– outputs; and (4) resistor divider on ADJ+/ADJ– for output voltage setting. Optional 100nF BYP+ and BYP– caps further reduce noise.
Does the LTC3265HDHC#PBF support independent enable/disable of its positive and negative output rails?
Yes. The LTC3265HDHC#PBF provides fully independent control: EN+ enables/disables the boost charge pump and LDO+, while EN– controls the inverting charge pump and LDO–. Both pins feature internal pull-downs, eliminating the need for external resistors - enabling flexible power sequencing in mixed-signal systems without cross-rail interference.
LTC3265HDHC#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 18-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Ratiometric
- Output Configuration:
- Positive and Negative (Dual Rail)
- Topology:
- Charge Pump
- Output Type:
- Fixed
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 32V
- Voltage - Output (Min/Fixed):
- -Vin, 2Vin
- Voltage - Output (Max):
- -
- Current - Output:
- 100mA
- Frequency - Switching:
- 50kHz ~ 500kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 18-DFN (5x3)
LTC3265HDHC#PBF FAQ
1.How can I place an order for LTC3265HDHC#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3265HDHC#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3265HDHC#PBF reliable?
The price and inventory of LTC3265HDHC#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3265HDHC#PBF is usually 5 days.
3.What payment methods are accepted for LTC3265HDHC#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3265HDHC#PBF transactions.
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4.How is shipping managed for LTC3265HDHC#PBF?
LTC3265HDHC#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3265HDHC#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3265HDHC#PBF?
For technical support, including LTC3265HDHC#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3265HDHC#PBF requirements.
6.How does Aetrix verify that LTC3265HDHC#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3265HDHC#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3265HDHC#PBF meets industry standards.
7.What is the process for return or replacement of LTC3265HDHC#PBF?
All LTC3265HDHC#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3265HDHC#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3265HDHC#PBF part is unused and in its original packaging.
Return procedure for LTC3265HDHC#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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