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Analog Devices Inc. LTC3265MPDHC#PBF
- Part No.:
- LTC3265MPDHC#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 18-WFDFN Exposed Pad
- Datasheet:
-
LTC3265MPDHC#PBF.pdf
- Description:
- IC REG CHARGE PUMP INV DL 18DFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,107
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Product details
Overview
LTC3265MPDHC#PBF from Analog Devices (formerly Linear Technology) is a low-noise dual-polarity power supply IC integrating a boost charge pump, an inverting charge pump, and two post-regulating LDOs - delivering ±15V outputs from a single 12V input with <100 µVRMS output noise, 135 µA quiescent current in Burst Mode®, and ±50 mA LDO output capability. It serves as a compact bipolar bias generator for precision analog signal chains in instrumentation and data acquisition systems.
For engineers reviewing the LTC3265MPDHC#PBF datasheet, LTC3265MPDHC#PBF pinout, LTC3265MPDHC#PBF application, or LTC3265MPDHC#PBF equivalent, key selection criteria include its –55°C to 150°C operating junction temperature range, programmable 50–500 kHz oscillator frequency via RT pin, dual LDO adjustability via ADJ+/ADJ–, and validated operation with ceramic capacitors only - critical for low-noise industrial sensor front-ends and high-reliability embedded systems.
Technical Context
The LTC3265MPDHC#PBF implements two independent charge pump topologies: a boost stage (CBST+, CBST–) generating up to 2×VIN_P, and an inverting stage (CINV+, CINV–) generating –VIN_N or –VOUT+, both selectable between constant-frequency (50–500 kHz) and Burst Mode® operation. Each pump feeds a dedicated low-noise LDO (LDO+, LDO–) with 1.2 V reference (ADJ+/ADJ–), enabling precise output voltage programming across wide input ranges (VIN_P: 4.5–16 V; VIN_N: 4.5–32 V).
Its control architecture uses MODE pin logic to select regulation mode (Burst vs. constant-frequency), EN+/EN– pins for independent enable/disable of positive/negative paths, and RT pin-based oscillator programming - all coordinated through internal logic that enforces soft-start, short-circuit limiting (220 mA/160 mA), and thermal shutdown (>175°C). The DFN package features exposed GND pad for thermal management and EMI reduction.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN_P Range | 4.5 V to 16 V - supports standard industrial 5 V, 12 V, and 15 V rails without external pre-regulation. |
| VIN_N Range | 4.5 V to 32 V - enables flexible negative rail generation from either main input or boosted VOUT+. |
| LDO Output Current | ±50 mA - sufficient to power op-amps, ADC drivers, and precision references in dual-supply circuits. |
| Quiescent Current (Burst) | 135 µA with both LDOs active - enables battery-backed or ultra-low-power standby modes. |
| Oscillator Frequency | 50 kHz to 500 kHz (RT-programmable) - allows trade-off between efficiency, ripple, and EMI filtering component size. |
| LDO Output Noise | 100 µVRMS (with 100 nF BYP+/- bypass) - meets requirements for 16-bit+ SAR ADC reference buffers and low-distortion audio stages. |
| Operating Temp Range | –55°C to +150°C (junction) - qualified for extended-temperature aerospace, downhole, and military applications. |
Pinout & Package
Package: 18-lead (5 mm × 3 mm × 0.75 mm) plastic DFN with exposed GND pad (Pin 19), thermally enhanced for θJA = 42°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CBST– (Pin 1) | Boost flying capacitor negative terminal | Connects to negative side of external flying cap; forms charge transfer path during boost phase. |
| CBST+ (Pin 2) | Boost flying capacitor positive terminal | Connects to positive side of flying cap; delivers charge to VOUT+ during transfer phase. |
| VIN_P (Pin 3) | Boost pump input supply | Primary input for boost stage; must be bypassed with ≥10 µF ceramic capacitor. |
| EN– (Pin 4) | Negative path enable control | Logic-high enables inverting pump and LDO–; internal 0.7 µA pull-down prevents floating. |
| BYP– (Pin 5) | LDO– reference bypass | Accepts 100 nF capacitor to ground to reduce LDO– output noise by stabilizing internal –1.2 V reference. |
| ADJ– (Pin 6) | LDO– feedback node | Serves as –1.2 V reference point; resistor divider from LDO– to GND sets output voltage per VLDO– = –1.2 × (R1/R2 + 1). |
| LDO– (Pin 7) | Negative regulated output | Delivers user-programmed negative voltage (–1.2 V to –32 V); requires ≥2 µF low-ESR ceramic capacitor to GND for stability. |
| VOUT– (Pin 8) | Inverting pump output | Provides –VIN_N (constant freq) or –0.94×VIN_N (Burst Mode); powers LDO– and supports direct use as unregulated rail. |
| CINV– (Pin 9) | Inverting flying capacitor positive terminal | Connects to positive side of inverting flying cap; critical for polarity inversion timing and efficiency. |
| CINV+ (Pin 10) | Inverting flying capacitor negative terminal | Connects to negative side of inverting flying cap; completes charge transfer loop for negative rail generation. |
| VIN_N (Pin 11) | Inverting pump input supply | Can be tied to VIN_P (asymmetric –VIN_P) or VOUT+ (symmetric –2×VIN_P); bypass with ≥10 µF ceramic cap. |
| RT (Pin 12) | Oscillator frequency set | 1.2 V-regulated node; resistor to GND programs switching frequency from 50 kHz to 500 kHz (GND = 500 kHz default). |
| EN+ (Pin 13) | Positive path enable control | Logic-high enables boost pump and LDO+; internal 0.7 µA pull-down ensures defined state when un-driven. |
| MODE (Pin 14) | Charge pump operating mode | High = Burst Mode® (low IQ, higher ripple); Low = constant-frequency (lower ripple, higher IQ); hysteresis prevents chatter. |
| BYP+ (Pin 15) | LDO+ reference bypass | Accepts 100 nF capacitor to ground to reduce LDO+ output noise by stabilizing internal +1.2 V reference. |
| ADJ+ (Pin 16) | LDO+ feedback node | Serves as +1.2 V reference point; resistor divider from LDO+ to GND sets output voltage per VLDO+ = 1.2 × (R1/R2 + 1). |
| LDO+ (Pin 17) | Positive regulated output | Delivers user-programmed positive voltage (1.2 V to 32 V); requires ≥2 µF low-ESR ceramic capacitor to GND for stability. |
| VOUT+ (Pin 18) | Boost pump output | Provides 2×VIN_P (constant freq) or 0.94×2×VIN_P (Burst Mode); powers LDO+ and supports direct use as unregulated rail. |
| GND (Pin 19, Exposed Pad) | System ground and thermal path | Must be soldered to PCB ground plane; provides primary thermal conduction path and EMI shielding. |
Key Features
| Feature | Design Value |
|---|---|
| Burst Mode® operation | Reduces total system IQ to 135 µA with both LDOs active - extends battery life in portable instrumentation without sacrificing regulation accuracy. |
| Dual independent enable pins (EN+/EN–) | Allows asymmetric power sequencing: e.g., enable LDO+ first for analog front-end bias, then LDO– after settling - prevents latch-up in mixed-signal ASICs. |
| RT-programmable oscillator | Enables EMI-sensitive designs to shift switching frequency away from critical bands (e.g., 100–200 kHz for audio) while maintaining stable regulation. |
| Stable with ceramic capacitors only | Eliminates need for tantalum or electrolytic bulk caps - improves long-term reliability and reduces board area in space-constrained modules. |
| Integrated soft-start | Prevents inrush current spikes on VOUT+/VOUT– during power-up - avoids triggering upstream current-limit protection in shared supply rails. |
| Short-circuit and thermal protection | Self-limits VOUT+ to 220 mA and VOUT– to 160 mA; shuts down above 175°C junction - protects downstream circuitry during fault conditions without external components. |
Applications
| Instrumentation Signal Chain Bias | Precision Data Acquisition Front-End |
|---|---|
Use Scenario: Powering dual-supply op-amps and reference buffers in handheld multimeters and portable oscilloscopes. IC Role / Device Role / Timing Role: Generates low-noise ±15 V rails from a single 12 V Li-ion battery pack, with Burst Mode® reducing standby current to extend battery life. Use Value: 100 µVRMS LDO noise ensures <0.001% THD+N in 16-bit ADC drivers; –55°C to 150°C rating supports operation in extreme environmental test chambers. | Use Scenario: Supplying isolated analog front-ends in industrial PLC I/O modules requiring galvanically separated ±12 V sensor excitation. IC Role / Device Role / Timing Role: Provides independently enabled positive and negative rails, allowing controlled power-up sequencing to prevent transient coupling into sensitive measurement nodes. Use Value: Dual EN+ and EN– pins enable staggered activation; ceramic-only stability simplifies layout in high-vibration environments where electrolytics degrade. |
| Low-Noise Audio DAC Reference | Aerospace Sensor Conditioning |
Use Scenario: Generating ultra-low-noise bias for high-fidelity audio DAC output stages in broadcast equipment. IC Role / Device Role / Timing Role: Delivers ±5 V rails with <100 µVRMS noise using BYP+/BYP– 100 nF bypass caps; RT pin set to 200 kΩ for 250 kHz switching - avoiding audible beat frequencies. Use Value: Measured output ripple <1 mVPP at 20 Hz–20 kHz ensures >110 dB SNR; constant-frequency mode eliminates switching artifacts in audio band. | Use Scenario: Powering radiation-tolerant op-amps and MEMS accelerometers in satellite attitude control subsystems. IC Role / Device Role / Timing Role: Operates across –55°C to +150°C junction range with no derating; exposed-pad DFN package enables direct thermal coupling to spacecraft chassis. Use Value: Qualified for extended temperature operation without burn-in; short-circuit protection maintains system integrity during single-event transients in orbit. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-polarity regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3261IMSE#PBF | Single-output (positive only), no inverting pump; 100 mA LDO, 60 µA IQ in Burst Mode | Cannot generate negative rail - requires external inverter or split-rail supply | Select when only positive bias needed and lower IQ is critical; not a functional substitute for LTC3265MPDHC#PBF's bipolar output. |
| MAX1759EUB+T | Single inverting charge pump + LDO (–1.2 V to –15 V); no boost stage; 100 mA output; 200 µA IQ | Lacks positive rail generation - requires separate positive supply or regulator | Choose when negative bias only is required and footprint is constrained; lacks dual-path integration and temperature range of LTC3265MPDHC#PBF. |
Compared with LTC3265MPDHC#PBF, LTC3261IMSE#PBF offers lower quiescent current but no negative output capability, while MAX1759EUB+T provides only inverting functionality - neither matches the integrated dual-polarity, wide-input, extended-temperature performance of LTC3265MPDHC#PBF in precision instrumentation.
Availability
LTC3265MPDHC#PBF is available at Aetrix Electronics and suitable for precision instrumentation, aerospace sensor conditioning, and industrial data acquisition systems requiring stable component supply across extended temperature ranges and low-noise bipolar power delivery.
Supply support for LTC3265MPDHC#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for the LTC portfolio.
The LTC3265MPDHC#PBF belongs to Linear's high-voltage, low-noise power management family - designed specifically for precision analog systems needing clean, programmable dual-rail supplies from single inputs in harsh thermal environments.
FAQ
What is the maximum allowable junction temperature for the LTC3265MPDHC#PBF?
The LTC3265MPDHC#PBF is rated for continuous operation up to +150°C junction temperature. Its thermal shutdown activates at approximately +175°C to protect against momentary overloads. The device is characterized and guaranteed across –55°C to +150°C, making it suitable for high-reliability applications where ambient temperatures exceed standard commercial limits. Derating guidelines apply above +125°C for long-term reliability.
Can the LTC3265MPDHC#PBF generate symmetric ±15 V outputs from a 12 V input?
Yes, the LTC3265MPDHC#PBF can generate symmetric ±15 V outputs from a 12 V input. Tie VIN_N to VOUT+ (not VIN_P), configure MODE for constant-frequency operation, set RT = GND for 500 kHz, and use resistor dividers on ADJ+/ADJ– to program LDO+ = +15 V and LDO– = –15 V. This configuration yields –VOUT+ = –2×12 V = –24 V at VOUT–, which the LDO– then regulates down to –15 V with low noise and high PSRR.
How does the RT pin affect switching frequency and output impedance in the LTC3265MPDHC#PBF?
The RT pin on the LTC3265MPDHC#PBF sets oscillator frequency from 50 kHz to 500 kHz via an external resistor to GND. Higher frequencies reduce effective open-loop output impedance (e.g., ~32 Ω at 500 kHz), improving load transient response and reducing required output capacitance. At lower frequencies (e.g., 50 kHz), ROL increases, limiting available average current and increasing ripple - making 500 kHz optimal for most precision applications unless EMI constraints dictate otherwise.
Is external compensation required for stability of the LTC3265MPDHC#PBF LDOs?
No external compensation is required for basic stability of the LTC3265MPDHC#PBF LDOs. The device is designed to be stable with ≥2 µF low-ESR ceramic capacitors on LDO+ and LDO– outputs. An optional 10 pF capacitor (COPT) may be added between ADJ+ and GND or ADJ– and GND to improve transient response, but this is application-specific and not mandatory. Stability is verified across temperature and load with standard ceramic caps only.
What protection features are built into the LTC3265MPDHC#PBF?
The LTC3265MPDHC#PBF integrates short-circuit current limiting (220 mA on VOUT+, 160 mA on VOUT–), thermal shutdown (>175°C junction), and undervoltage lockout (3.4 V rising on VIN_P). It also includes soft-start circuitry for both charge pumps and LDOs to limit inrush current, and internal pull-downs on EN+/EN–/MODE pins to prevent undefined states. These features operate autonomously without external components or configuration.
LTC3265MPDHC#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 18-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Ratiometric
- Output Configuration:
- Positive and Negative (Dual Rail)
- Topology:
- Charge Pump
- Output Type:
- Fixed
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 4.5V
- Voltage - Input (Max):
- 32V
- Voltage - Output (Min/Fixed):
- -Vin, 2Vin
- Voltage - Output (Max):
- -
- Current - Output:
- 100mA
- Frequency - Switching:
- 50kHz ~ 500kHz
- Synchronous Rectifier:
- No
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 18-DFN (5x3)
LTC3265MPDHC#PBF FAQ
1.How can I place an order for LTC3265MPDHC#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3265MPDHC#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3265MPDHC#PBF reliable?
The price and inventory of LTC3265MPDHC#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3265MPDHC#PBF is usually 5 days.
3.What payment methods are accepted for LTC3265MPDHC#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3265MPDHC#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3265MPDHC#PBF?
LTC3265MPDHC#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3265MPDHC#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3265MPDHC#PBF?
For technical support, including LTC3265MPDHC#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3265MPDHC#PBF requirements.
6.How does Aetrix verify that LTC3265MPDHC#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3265MPDHC#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3265MPDHC#PBF meets industry standards.
7.What is the process for return or replacement of LTC3265MPDHC#PBF?
All LTC3265MPDHC#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3265MPDHC#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3265MPDHC#PBF part is unused and in its original packaging.
Return procedure for LTC3265MPDHC#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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