Analog Devices Inc. LTC3315BEV#TRMPBF
- Part No.:
- LTC3315BEV#TRMPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 12-VFQFN Exposed Pad
- Datasheet:
-
LTC3315BEV#TRMPBF.pdf
- Description:
- IC REG BUCK ADJ 2A/2A DL 12LQFN
- Quantity:
- Payment:

- Shipping:

Inventory:654
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3315BEV#TRMPBF from Analog Devices is a dual monolithic synchronous step-down DC/DC converter IC delivering two independent 2A outputs from a 2.25V–5.5V input, operating at 6MHz with 25ns minimum on-time and ±1% output voltage accuracy. It integrates two buck regulators in a single 2mm × 2mm LQFN-12 package with exposed pad, targeting space-constrained POL applications for FPGA core supplies and telecom infrastructure.
For engineers reviewing the LTC3315BEV#TRMPBF datasheet, LTC3315BEV#TRMPBF pinout, LTC3315BEV#TRMPBF application, or LTC3315BEV#TRMPBF equivalent, key selection criteria include dual 2A output capability, 6MHz synchronized switching, 500mV precision feedback threshold, Burst Mode® efficiency at light loads, and AEC-Q100 qualification for automotive-grade reliability.
Technical Context
The LTC3315BEV#TRMPBF implements peak current mode control with dual 180° out-of-phase buck regulators sharing a common oscillator and MODE/SYNC interface. Its internal 500mV reference regulates both outputs independently via FB1/FB2 pins, while integrated 19mΩ NMOS and 75mΩ PMOS switches enable high-efficiency operation across 0.5V–VIN output range.
It supports three operating modes-forced continuous, pulse-skipping, and Burst Mode®-selected via the MODE/SYNC pin, with automatic PLL-based synchronization to external clocks from 3MHz to 10MHz. Thermal shutdown triggers at 165°C with 5°C hysteresis, and PGOOD asserts low on output undervoltage (<97% VOUT), overvoltage (>110% VOUT), or thermal fault after 120µs filtering.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.25V to 5.5V - supports single-supply operation from 3.3V or 5V rails without intermediate regulation. |
| Output Voltage Range | 0.5V to VIN - enables direct generation of sub-1V FPGA core voltages with tight regulation. |
| Max Output Current (per channel) | 2A - sufficient for powering dual-core processors or memory I/O banks with margin. |
| Switching Frequency | 6MHz (default), synchronizable 3–10MHz - enables use of <330nH inductors and compact ceramic capacitors. |
| Feedback Voltage Accuracy | ±1% over –40°C to 125°C - ensures stable core voltage under thermal stress in industrial environments. |
| Quiescent Current (both bucks enabled, Burst Mode) | 70µA (typ) - extends battery life in always-on subsystems without sacrificing startup speed. |
| Minimum On-Time | 25ns - allows high step-down ratios (e.g., 5.5V→0.8V at 6MHz) without pulse skipping instability. |
| Shutdown Current | 1.2µA - meets ultra-low-power system standby requirements. |
Pinout & Package
Package: 12-lead LQFN (2mm × 2mm × 0.74mm) with exposed GND pad (Pin 13), MSL 3, rated for –40°C to 125°C junction temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1 (Pin 1) | Enable input for Buck 1 | Active-high with 400mV precision threshold; supports resistor-divider sequencing from upstream rail. |
| FB1 (Pin 2) | Feedback input for Buck 1 | Regulates VOUT1 to 500mV; connects to resistor divider mid-point for programmable output voltage. |
| FB2 (Pin 3) | Feedback input for Buck 2 | Regulates VOUT2 to 500mV; independent of FB1 for asymmetric dual-output configurations. |
| EN2 (Pin 4) | Enable input for Buck 2 | Independent control enables staggered power-up or dynamic rail disabling. |
| PGOOD (Pin 5) | Open-drain power-good indicator | Asserts low if either enabled buck falls below 97% VOUT, exceeds 110% VOUT, or thermal shutdown occurs. |
| SW2 (Pin 6) | Switch node for Buck 2 | Connects to inductor; requires short, wide PCB trace to minimize EMI and switching losses. |
| VIN (Pins 7, 10) | Input supply inputs | Dual VIN pins reduce IR drop and improve thermal distribution; must be bypassed locally with low-ESR caps. |
| GND (Pins 8, 9, 13) | Ground terminals | Exposed pad (Pin 13) is primary thermal path; must be soldered to solid ground plane for θJA = 51°C/W. |
| SW1 (Pin 11) | Switch node for Buck 1 | 180° out-of-phase with SW2 to reduce input ripple current and simplify input capacitor sizing. |
| MODE/SYNC (Pin 12) | Mode selection & sync input | Configures operating mode (Burst/Pulse-skip/Forced Continuous) or accepts external 3–10MHz clock for EMI control. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 2A synchronous buck regulators | Reduces board area by 40% vs discrete solutions while maintaining independent output control and sequencing. |
| 6MHz fixed-frequency operation with 25ns min on-time | Enables 1.0µH or smaller inductors and eliminates need for external compensation components. |
| Burst Mode® with 70µA quiescent current (both channels) | Extends runtime in battery-powered systems where one or both rails operate at light load >80% of time. |
| 180° phase interleaving | Cuts input RMS current by ~30%, allowing smaller input bulk capacitors and reducing EMI filter size. |
| AEC-Q100 qualified (Grade E, –40°C to 125°C) | Validated for automotive infotainment and ADAS domain controllers without derating. |
| Integrated output overvoltage protection | Shuts off PMOS within nanoseconds if FB exceeds 110% VOUT, preventing damage to downstream logic. |
Applications
| FPGA Core & I/O Supply | Telecom Point-of-Load (POL) |
|---|---|
Use Scenario: Powering Xilinx Artix-7 FPGA with separate 1.0V core and 1.8V I/O rails from a 3.3V backplane supply. IC Role / Device Role / Timing Role: Dual-channel DC/DC regulator providing tightly regulated, low-noise, fast-transient power with independent enable control. Use Value: Eliminates need for two discrete buck ICs and associated passives, reducing BOM count by 32% and layout area by 45%. |
Use Scenario: Generating 1.2V and 2.5V rails for optical transceiver modules in 5G baseband units. IC Role / Device Role / Timing Role: High-frequency POL regulator delivering fast load-step response (<10µs) to handle bursty data traffic. Use Value: 6MHz switching enables <220nH inductors and 10µF ceramic output caps, meeting stringent size constraints in pluggable modules. |
| Automotive Infotainment SoC | Industrial PLC CPU Module |
Use Scenario: Supplying 1.1V CPU core and 1.8V GPU rails for NXP i.MX8M Plus in head-unit designs. IC Role / Device Role / Timing Role: AEC-Q100 qualified dual buck managing cold-crank (4.5V) to hot-idle (14V) input transients. Use Value: 2.25V minimum VIN and 100% duty cycle operation ensure uninterrupted core power during battery dip events. |
Use Scenario: Providing 3.3V and 5.0V auxiliary rails for ARM Cortex-A53-based controller in DIN-rail mounted PLC. IC Role / Device Role / Timing Role: Industrial-grade dual regulator supporting extended temperature operation and long-term reliability. Use Value: –40°C to 125°C rating and 1.2µA shutdown current meet EN 61000-6-2 immunity and energy-saving mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62150ARGTR | Single 3A buck; no dual-output capability; 2.5–6V input; 1.2MHz max frequency. | Requires two ICs to match LTC3315BEV#TRMPBF's dual 2A functionality; larger solution size. | Select only when cost sensitivity outweighs board space constraints and dual-rail coordination is unnecessary. |
| ISL8026IRZ-T7A | Dual 3A buck; 2.7–5.5V input; 500kHz–4MHz frequency; no Burst Mode®; 1.2% VFB accuracy. | Lower switching frequency increases inductor size; lacks 25ns min on-time for high-ratio conversion. | Prefer for high-current, lower-frequency designs where thermal management dominates over footprint. |
Compared with TPS62150ARGTR and ISL8026IRZ-T7A, the LTC3315BEV#TRMPBF uniquely delivers dual 2A outputs in a 2mm × 2mm package with 6MHz operation, 25ns minimum on-time, and Burst Mode® efficiency-enabling the smallest possible POL solution for multi-rail embedded systems.
Availability
LTC3315BEV#TRMPBF is available at Aetrix Electronics and suitable for FPGA core supplies, telecom point-of-load systems, and automotive infotainment applications requiring stable component supply, AEC-Q100 compliance, and high-frequency switching performance.
Supply support for LTC3315BEV#TRMPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving industrial, automotive, communications, and healthcare markets.
The LTC3315B product line delivers highly integrated, high-frequency dual buck regulators optimized for space-constrained, high-efficiency point-of-load applications in servers, optical networking, and automotive electronics.
FAQ
What is the maximum supported switching frequency for LTC3315BEV#TRMPBF?
The LTC3315BEV#TRMPBF supports synchronization to external clocks from 3MHz to 10MHz. Its internal oscillator defaults to 6MHz, and the minimum on-time of 25ns ensures stable operation even at the upper end of this range. Operation above 10MHz is not guaranteed and may cause pulse skipping or regulation loss.
Does LTC3315BEV#TRMPBF support independent enable control for each buck channel?
Yes, LTC3315BEV#TRMPBF provides fully independent enable inputs: EN1 (Pin 1) controls Buck 1 and EN2 (Pin 4) controls Buck 2. Each has a precision 400mV threshold and can be driven directly by a microcontroller GPIO or sequenced using resistor dividers from upstream rails.
How does the PGOOD pin behave when only one buck regulator is enabled?
When only one buck is enabled, the PGOOD pin remains high only if that enabled buck maintains its output within 97–110% of regulation. If the enabled buck fails (e.g., due to overload or UVLO), PGOOD pulls low. If both bucks are disabled, PGOOD is actively pulled low regardless of input voltage status.
What thermal performance can be expected from LTC3315BEV#TRMPBF in a standard 4-layer PCB?
With the exposed GND pad (Pin 13) soldered to a 1-in² internal ground plane on a 4-layer board, LTC3315BEV#TRMPBF achieves θJA = 51°C/W. At 2A per channel and 3.3V input, typical power dissipation is ~0.4W, resulting in ~20°C rise above ambient-well within the –40°C to 125°C operating range.
Can LTC3315BEV#TRMPBF operate with an input voltage below 2.25V?
No. The absolute minimum input voltage for LTC3315BEV#TRMPBF is 2.25V, as specified in the Absolute Maximum Ratings and Electrical Characteristics tables. Operation below this threshold causes undervoltage lockout (UVLO) activation, disabling both bucks until VIN rises above 2.15V (typical hysteresis).
LTC3315BEV#TRMPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 12-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.25V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.5V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 2A, 2A
- Frequency - Switching:
- 6MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-LQFN (2x2)
LTC3315BEV#TRMPBF FAQ
1.How can I place an order for LTC3315BEV#TRMPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3315BEV#TRMPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3315BEV#TRMPBF reliable?
The price and inventory of LTC3315BEV#TRMPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3315BEV#TRMPBF is usually 5 days.
3.What payment methods are accepted for LTC3315BEV#TRMPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3315BEV#TRMPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3315BEV#TRMPBF?
LTC3315BEV#TRMPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3315BEV#TRMPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3315BEV#TRMPBF?
For technical support, including LTC3315BEV#TRMPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3315BEV#TRMPBF requirements.
6.How does Aetrix verify that LTC3315BEV#TRMPBF is sourced from the original manufacturer or authorized distributors?
All LTC3315BEV#TRMPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3315BEV#TRMPBF meets industry standards.
7.What is the process for return or replacement of LTC3315BEV#TRMPBF?
All LTC3315BEV#TRMPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3315BEV#TRMPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3315BEV#TRMPBF part is unused and in its original packaging.
Return procedure for LTC3315BEV#TRMPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3315BEV#TRMPBF Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

