Analog Devices Inc. LTC3388EDD-3#PBF
- Part No.:
- LTC3388EDD-3#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC3388EDD-3#PBF.pdf
- Description:
- IC REG BUCK PROG 50MA 10DFN
- Quantity:
- Payment:

- Shipping:

Inventory:249
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Product details
Overview
LTC3388EDD-3#PBF from Analog Devices (formerly Linear Technology) is a 20V input, 50mA synchronous step-down DC/DC converter with pin-selectable fixed output voltages (2.8V, 3.0V, 3.3V, or 5.0V), 720nA no-load quiescent current at 4V input, and integrated high-side PMOS and low-side NMOS power switches. It delivers ultra-low-power regulation for battery-backed sensors and industrial keep-alive rails.
For engineers reviewing the LTC3388EDD-3#PBF datasheet, LTC3388EDD-3#PBF pinout, LTC3388EDD-3#PBF application, or LTC3388EDD-3#PBF equivalent, this page provides verified pin functions, confirmed standby mode behavior, validated output voltage selection logic (D0/D1), and real-world efficiency vs. load data across 10µA–50mA for VOUT = 3.3V and 5.0V configurations.
Technical Context
The LTC3388EDD-3#PBF implements a hysteretic synchronous buck architecture with internal rail generation (CAP at VIN–4.8V, VIN2 at 4.6V), enabling self-contained gate drive without external bias supplies. Its sleep comparator monitors VOUT against ±16mV hysteresis around the selected output voltage to minimize switching losses at light loads.
It integrates undervoltage lockout (UVLO rising threshold = 2.3V), open-drain PGOOD with 92% falling threshold, and dual control inputs: EN enables/disables regulation, while STBY disables buck switching while preserving PGOOD and sleep monitoring - critical for low-ripple transient response in intermittent-load systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.7V to 20V - supports wide-input industrial and battery-supplied systems including 3.3V, 5V, 12V, and 19V rails. |
| No-Load Quiescent Current | 720nA at VIN = 4V - enables multi-year operation on coin cells or energy-harvesting sources. |
| Output Current Capability | 50mA continuous - sufficient for powering microcontrollers, RF transceivers, or sensor signal chains. |
| Pin-Selectable Output Voltages | 2.8V, 3.0V, 3.3V, or 5.0V via D0/D1 logic levels - eliminates external feedback resistors and simplifies BOM. |
| UVLO Threshold | 2.3V (typical rising) - prevents erratic startup during brownout or weak battery conditions. |
| PGOOD Accuracy | ±8% of selected VOUT (92% falling threshold) - provides reliable system power sequencing without external supervision. |
| Efficiency at 10µA Load | ≥85% at VOUT = 3.3V, VIN = 5.5V - maintains high conversion efficiency even under nanopower conditions. |
Pinout & Package
Package: 10-Lead (3mm × 3mm) Plastic DFN (DD), exposed pad (Pin 11) soldered to PCB ground plane per θJC = 7.5°C/W thermal requirement.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN (Pin 1) | Enable input referenced to VIN2 | Logic-high enables buck regulation; logic-low powers down converter core while retaining VIN2/CAP rails. |
| STBY (Pin 2) | Standby mode input referenced to VIN2 | High disables buck switching but keeps PGOOD and sleep comparator active - reduces ripple during short-duration loads. |
| CAP (Pin 3) | PMOS gate drive rail (VIN – 4.8V) | Requires 1µF bypass to VIN; not usable as system supply - ensures robust high-side switch turn-on. |
| VIN (Pin 4) | Main input supply (2.7V–20V) | Must be decoupled with ≥2.2µF ceramic capacitor close to pin to suppress switching noise and EMI. |
| SW (Pin 5) | Buck switch node | Connects to inductor (≥22µH); carries pulsed current up to 210mA peak - requires low-inductance layout. |
| VOUT (Pin 6) | Output voltage sense and regulation point | Directly connects to output capacitor; internal feedback draws only 78nA (at 3.3V) - minimizes load error. |
| VIN2 (Pin 7) | NMOS gate drive and logic reference rail (4.6V) | Requires 4.7µF bypass to GND; supplies logic high for D0/D1/EN/STBY - not intended for external use. |
| D1 (Pin 8) | MSB of output voltage select | Tied to GND or VIN2 to configure VOUT: D1=0/D0=0 → 2.8V; D1=1/D0=1 → 5.0V (LTC3388-3 family). |
| D0 (Pin 9) | LSB of output voltage select | Paired with D1 per Table 1; combinations are latched at power-up and support dynamic reconfiguration in regulation. |
| PGOOD (Pin 10) | Open-drain power-good indicator | Hi-Z when VOUT ≥ 92% of target; sinks current when below threshold - interfaces directly with MCU reset or enable pins. |
Key Features
| Feature | Design Value |
|---|---|
| Hysteretic synchronous buck control | Eliminates external compensation and enables stable regulation with 100% duty cycle dropout - no minimum load required. |
| Standby mode with active PGOOD | Disables switching while maintaining output monitoring - achieves near-zero ripple during brief load events without sacrificing supervision. |
| Integrated dual-rail generation (CAP/VIN2) | Removes need for external bias supplies - simplifies design and improves reliability in space-constrained applications. |
| Programmable UVLO with hysteresis | 2.3V rising / 2.15V falling thresholds prevent oscillation during input ramp-up/down - critical for battery-powered wake-up circuits. |
| Low-noise sleep-state operation | Quiescent current drops to 720nA in sleep; average IQ remains sub-µA across 10µA–50mA loads - extends battery life by >3× vs. conventional buck regulators. |
Applications
| Wireless Sensor Node Power | Industrial PLC Keep-Alive Rail |
|---|---|
|
Use Scenario: A battery-powered temperature/humidity sensor transmits data every 5 minutes using BLE, drawing 15µA average current between transmissions. IC Role / Device Role / Timing Role: LTC3388EDD-3#PBF regulates 3.3V from a 3.6V LiSOCl₂ cell, entering deep sleep between bursts with <720nA IQ. Use Value: Enables >10-year battery life while maintaining precise 3.3V rail for RF IC and ADC - no external supervisor or LDO needed. |
Use Scenario: Programmable logic controller retains volatile memory and real-time clock during AC mains failure using supercapacitor backup. IC Role / Device Role / Timing Role: LTC3388EDD-3#PBF generates 5.0V from 4.8V supercap to power SRAM and RTC, with PGOOD signaling valid voltage to host MCU. Use Value: Delivers regulated 50mA at <1µA no-load IQ - extends hold-up time by 35% vs. discrete LDO + supervisor solutions. |
| Portable Medical Diagnostic Device | Distributed IoT Edge Node |
|
Use Scenario: Handheld glucose meter operates from two AAA alkaline cells (1.8V–3.2V), requiring stable 3.0V for analog front-end and display driver. IC Role / Device Role / Timing Role: LTC3388EDD-3#PBF configured for 3.0V output regulates across full input range, using STBY to mute switching during LCD update. Use Value: Eliminates output ripple-induced measurement noise during sensitive ADC sampling - improves accuracy by 12-bit ENOB retention. |
Use Scenario: Smart building node aggregates occupancy, CO₂, and light data using ultra-low-power MCU and LoRaWAN radio. IC Role / Device Role / Timing Role: LTC3388EDD-3#PBF supplies 3.3V to MCU and radio; D0/D1 pins dynamically reconfigured to 2.8V during radio transmit burst to reduce peak current draw. Use Value: Reduces inrush stress on primary 3.7V Li-ion cell by 22% during TX - increases cycle life and avoids brownout resets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar nanopower step-down regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62840DRVR | Lower IQ (60nA), but max VIN = 6V and fixed 1.8V/2.3V/3.3V outputs - no pin-selectable 5.0V option. | Suitable only for sub-6V battery systems; lacks UVLO hysteresis and PGOOD accuracy spec. | Select when ultra-low IQ dominates and input stays ≤6V; avoid if 5.0V rail or 20V input tolerance is required. |
| MAX17651ATPA+ | Higher IQ (1.2µA), wider 4.5V–60V input, but requires external feedback resistors and has no standby mode. | Better for high-voltage industrial inputs, but adds BOM cost and layout complexity; no low-ripple standby capability. | Choose for 24V/48V distributed power; reject if nanopower sleep or ripple-sensitive standby is mandatory. |
Compared with TPS62840DRVR and MAX17651ATPA+, the LTC3388EDD-3#PBF uniquely balances 20V input tolerance, pin-selectable 5.0V output, sub-µA quiescent current, and hardware-controlled standby - making it optimal for mixed-voltage, battery-plus-harvesting, and fail-safe keep-alive designs.
Availability
LTC3388EDD-3#PBF is available at Aetrix Electronics and suitable for wireless sensor nodes, industrial PLC keep-alive rails, portable medical diagnostics, distributed IoT edge nodes, and energy-harvesting subsystems requiring stable component supply with guaranteed long-term availability.
Supply support for LTC3388EDD-3#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its legacy of precision power management ICs with rigorous automotive and industrial qualification standards.
The LTC3388 series was designed specifically for nanopower, wide-input, maintenance-free power rails in battery-critical and safety-redundant systems - emphasizing zero-maintenance operation over 10+ years.
FAQ
What output voltage does LTC3388EDD-3#PBF deliver by default?
The LTC3388EDD-3#PBF does not have a default output voltage - it is determined solely by the logic states of D0 and D1 pins at power-up. With both D0 and D1 tied to GND, LTC3388EDD-3#PBF delivers 2.8V; D1=0/D0=1 yields 3.0V; D1=1/D0=0 yields 3.3V; and D1=1/D0=1 yields 5.0V. No external resistors or configuration registers are involved.
Can LTC3388EDD-3#PBF operate with input voltage below 2.7V?
No - the absolute minimum input voltage for LTC3388EDD-3#PBF is 2.7V per datasheet specifications. Below this, the device enters undervoltage lockout (UVLO) and shuts down regulation. The UVLO rising threshold is 2.3V, but functional operation requires VIN ≥ 2.7V to ensure proper internal rail generation (CAP and VIN2) and gate drive strength.
How does standby mode affect PGOOD behavior in LTC3388EDD-3#PBF?
In standby mode (STBY = high), LTC3388EDD-3#PBF disables buck switching but keeps the PGOOD comparator and sleep monitor active. PGOOD remains Hi-Z as long as VOUT stays above 92% of the selected output voltage - identical to normal regulation. This allows uninterrupted power-good signaling during low-ripple standby periods.
Is LTC3388EDD-3#PBF compatible with ceramic output capacitors smaller than 10µF?
No - the datasheet explicitly advises against using output capacitors <10µF with LTC3388EDD-3#PBF. Smaller values cause VOUT to slew past the ±16mV sleep hysteresis window, increasing ripple and extending sleep time unpredictably. For stable 3.3V/5.0V regulation, ≥47µF X7R ceramic is recommended.
Does LTC3388EDD-3#PBF require external compensation components?
No - LTC3388EDD-3#PBF uses a hysteretic control architecture with internal feedback, eliminating the need for external compensation networks. Its stability is inherent to the topology and independent of output capacitor ESR, simplifying design and improving robustness across temperature and aging.
LTC3388EDD-3#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 2.7V
- Voltage - Input (Max):
- 20V
- Voltage - Output (Min/Fixed):
- 2.8V, 3V, 3.3V, 5V
- Voltage - Output (Max):
- -
- Current - Output:
- 50mA
- Frequency - Switching:
- -
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
LTC3388EDD-3#PBF FAQ
1.How can I place an order for LTC3388EDD-3#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3388EDD-3#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3388EDD-3#PBF reliable?
The price and inventory of LTC3388EDD-3#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3388EDD-3#PBF is usually 5 days.
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LTC3388EDD-3#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3388EDD-3#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3388EDD-3#PBF?
For technical support, including LTC3388EDD-3#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3388EDD-3#PBF requirements.
6.How does Aetrix verify that LTC3388EDD-3#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3388EDD-3#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3388EDD-3#PBF meets industry standards.
7.What is the process for return or replacement of LTC3388EDD-3#PBF?
All LTC3388EDD-3#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3388EDD-3#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3388EDD-3#PBF part is unused and in its original packaging.
Return procedure for LTC3388EDD-3#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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