Analog Devices Inc. LTC3407EDD-3#PBF
- Part No.:
- LTC3407EDD-3#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC3407EDD-3#PBF.pdf
- Description:
- IC REG BUCK 1.8V/3.3V DL 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3407EDD-3#PBF from Analog Devices (formerly Linear Technology) is a dual-channel synchronous step-down DC/DC converter with fixed 1.8V/0.8A and 3.3V/0.8A outputs, operating from 3.3V to 5.5V input at 2.25MHz switching frequency. It integrates 0.35Ω P-channel and 0.30Ω N-channel internal MOSFETs, delivers 40μA quiescent current in active mode, and supports Burst Mode® for >95% efficiency at light loads - deployed in portable digital cameras and cellular handsets.
For engineers reviewing the LTC3407EDD-3#PBF datasheet, LTC3407EDD-3#PBF pinout, LTC3407EDD-3#PBF application, or LTC3407EDD-3#PBF equivalent, key selection criteria include verified dual-output regulation accuracy (±2% over –40°C to 85°C), confirmed 10-lead 3mm × 3mm DFN package with exposed PGND pad, validated 2.25MHz constant-frequency operation with external synchronization capability, and documented trade-offs between Burst Mode® (high efficiency) and pulse-skipping mode (low noise).
Technical Context
The LTC3407EDD-3#PBF employs a current-mode control architecture with shared 2.25MHz oscillator across both channels, enabling in-phase switching and precise load transient response. Each channel features independent RUN enable inputs, dedicated SW nodes, and internal 0.6V reference-based feedback via VOUT1/VOUT2 pins with integrated resistive dividers.
It implements dual low-power operating modes: Burst Mode® (activated by pulling MODE/SYNC to VIN) achieves 40μA total quiescent current and >90% efficiency at 1mA load, while pulse-skipping mode (MODE/SYNC grounded) maintains constant-frequency operation down to sub-mA loads with <20mVpp output ripple. Dropout operation enables 100% duty cycle with continuous P-channel switch conduction when VIN approaches VOUT.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 3.3V to 5.5V - supports single-cell Li-ion (fully charged) and regulated 3.3V/5V rails without external pre-regulation. |
| VOUT1 / VOUT2 | 1.8V ±2% / 3.3V ±2% - factory-trimmed outputs eliminate need for external feedback resistors in standard configurations. |
| Switching Frequency | 2.25MHz (±25%) - enables use of 2.2μH inductors and 10μF ceramic capacitors with ≤1.0mm profile. |
| Peak Switch Current | 1.2A per channel - supports 800mA continuous output with margin for transient peaks and thermal derating. |
| IQ (Active) | 40μA total - enables >100-hour battery life in always-on portable devices with dual-rail power. |
| RDS(ON) | 0.35Ω (P-ch) / 0.30Ω (N-ch) - reduces conduction loss to <25mW per channel at 800mA, minimizing thermal rise in DFN package. |
| Shutdown IQ | <1μA - ensures negligible battery drain during system sleep states. |
Pinout & Package
Package: 10-lead 3mm × 3mm plastic DFN with exposed power ground pad (Pin 11), thermally enhanced for ≤40°C/W junction-to-ambient operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUT1 (Pin 1) | Channel 1 feedback node | Internally connected to 0.6V reference comparator; sets 1.8V output via internal 240k/120k divider - no external resistors required. |
| RUN1 (Pin 2) | Channel 1 enable input | Active-high logic: ≥1.5V enables regulator; ≤0.3V disables with <1μA leakage - supports independent power sequencing. |
| VIN (Pin 3) | Main power input | Supplies both channels and internal circuitry; requires local 10μF ceramic decoupling to minimize high-frequency noise coupling. |
| SW1 (Pin 4) | Channel 1 switch node | Connects to inductor; swings from VIN to GND at 2.25MHz - must be routed with minimal loop area to reduce EMI. |
| GND (Pin 5) | Analog ground reference | Separate from PGND; connects to PCB ground plane for signal integrity - not internally bonded to exposed pad. |
| MODE/SYNC (Pin 6) | Mode select & sync input | Configures Burst Mode® (VIN), pulse-skipping (GND), or synchronizes to external 2.25MHz clock - no pull-up/down required. |
| SW2 (Pin 7) | Channel 2 switch node | Identical function to SW1; independent inductor connection enables separate LC filtering for 3.3V rail. |
| POR (Pin 8) | Power-on reset output | Open-drain output pulled low if either VOUT drops >8.5% below regulation; releases after 262,144 cycles (~117ms) when both rails are stable. |
| RUN2 (Pin 9) | Channel 2 enable input | Independent enable for 3.3V rail; allows staggered startup or dynamic rail disable during low-power states. |
| VOUT2 (Pin 10) | Channel 2 feedback node | Internally divided to 0.6V reference for 3.3V output (270k/60k ratio) - eliminates external resistor network. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent enable inputs (RUN1/RUN2) | Enables flexible power sequencing - e.g., 1.8V core rail enabled before 3.3V I/O rail to meet processor boot requirements. |
| Burst Mode® operation | Reduces total quiescent current to 40μA while maintaining regulation, extending battery runtime in standby without compromising wake-up latency. |
| Integrated 0.6V reference with internal dividers | Eliminates four external feedback resistors, saving PCB area and reducing BOM count while ensuring ±2% output accuracy over temperature. |
| Externally synchronizable 2.25MHz oscillator | Prevents beat frequencies in multi-regulator systems; allows clock alignment with baseband processors or RF transceivers to minimize conducted EMI. |
| 100% duty cycle dropout operation | Maintains regulated output down to VIN = VOUT + ILOAD × RDS(ON), critical for Li-ion battery discharge curves where voltage falls from 4.2V to 3.0V. |
Applications
| Digital Camera Core Power | Cellular Phone Baseband |
|---|---|
Use Scenario: Powers image sensor (1.8V) and ISP (3.3V) in compact camera modules with tight height constraints. IC Role / Device Role / Timing Role: Dual-output buck regulator delivering tightly regulated, low-noise rails with fast load transient response to handle burst capture current spikes. Use Value: 2.25MHz switching enables 2.2μH inductors and 10μF ceramics, achieving <1.0mm profile while sustaining >92% efficiency at 500mA load per rail. | Use Scenario: Supplies application processor core (1.8V) and memory interface (3.3V) in GSM/UMTS handsets during active call mode. IC Role / Device Role / Timing Role: Synchronous dual buck providing independent enable control and POR signaling to coordinate SoC power-up sequence. Use Value: 40μA quiescent current extends talk time; Burst Mode® maintains >88% efficiency at 10mA standby load without audible switching noise. |
| Portable Media Player Audio | Wireless Modem Interface |
Use Scenario: Generates clean 1.8V DAC supply and 3.3V codec I/O rail in MP3 players with sensitive analog audio paths. IC Role / Device Role / Timing Role: Dual buck with pulse-skipping mode selected via grounded MODE/SYNC pin to suppress switching ripple in audio band. Use Value: <20mVpp output ripple at 100mA load prevents audible artifacts; 0.35Ω/0.30Ω RDS(ON) minimizes thermal coupling into adjacent analog circuitry. | Use Scenario: Powers WLAN/BT combo chip (1.8V core) and Ethernet PHY (3.3V) in DSL/cable modems with shared 5V input bus. IC Role / Device Role / Timing Role: Dual buck with synchronized 2.25MHz operation prevents interference with 2.4GHz RF bands and 100BASE-TX signaling. Use Value: External clock sync eliminates heterodyne tones; 10-lead DFN package simplifies layout in space-constrained modem PCBs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62125DSGR | Single-channel, adjustable 0.9–3.6V output; 3MHz switching; 1.2A max; no integrated POR or SYNC pin. | Requires two ICs for dual-rail design; lacks power-good signaling and external clock sync. | Select only when needing higher frequency or adjustable outputs - not a drop-in replacement. |
| MAX17504ATP+T | Dual-channel, but 4.5–60V input range; 600kHz max; 2A per channel; requires external feedback resistors and MOSFETs. | Designed for industrial/high-voltage apps; larger solution size due to external FETs and compensation components. | Choose for wide-input systems (>12V); avoid for portable 3.3–5.5V battery-powered designs. |
Compared with TPS62125DSGR and MAX17504ATP+T, the LTC3407EDD-3#PBF uniquely integrates fixed 1.8V/3.3V outputs, POR, MODE/SYNC, and 2.25MHz operation in a 3mm × 3mm DFN - delivering smallest footprint and lowest component count for portable dual-rail applications.
Availability
LTC3407EDD-3#PBF is available at Aetrix Electronics and suitable for portable media players, digital cameras, cellular handsets, wireless modems, and PC card applications requiring stable component supply and long-term production continuity.
Supply support for LTC3407EDD-3#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors.
The LTC3407 family was designed specifically for space-constrained portable electronics requiring dual low-voltage rails with ultra-low quiescent current and minimal external components - targeting battery-powered imaging, communication, and multimedia devices.
FAQ
What is the guaranteed output voltage accuracy of the LTC3407EDD-3#PBF over temperature?
The LTC3407EDD-3#PBF guarantees ±2% output voltage accuracy for both VOUT1 (1.8V) and VOUT2 (3.3V) across the full –40°C to 85°C operating temperature range, as confirmed by electrical characterization and statistical process controls per datasheet Note 2. This accuracy is achieved using factory-trimmed internal feedback dividers, eliminating tolerance stack-up from external resistors.
Can the LTC3407EDD-3#PBF operate with only one channel enabled?
Yes, the LTC3407EDD-3#PBF supports independent channel operation: pulling RUN1 low disables Channel 1 (1.8V) while leaving Channel 2 (3.3V) active, and vice versa. When one channel is disabled, the POR pin remains low since regulation is lost on that rail - this behavior is explicitly defined in the PIN FUNCTIONS section of the datasheet.
What is the maximum achievable efficiency of the LTC3407EDD-3#PBF and under what conditions?
The LTC3407EDD-3#PBF achieves up to 95% peak efficiency at 500mA load per channel with VIN = 3.6V, as measured in Burst Mode® operation per Figure 34073 TA01b. Efficiency exceeds 90% from 10mA to 800mA per channel, dropping to ~85% at 1mA due to fixed gate charge losses dominating at ultra-light loads.
How does the MODE/SYNC pin affect the LTC3407EDD-3#PBF's switching behavior in pulse-skipping mode?
In pulse-skipping mode (MODE/SYNC tied to GND), the LTC3407EDD-3#PBF maintains 2.25MHz switching down to ~1mA load, then begins skipping cycles to maintain regulation. Connecting the SW node to MODE/SYNC reduces frequency by ~30% (to ~1.6MHz), improving light-load efficiency by lowering gate charge losses - a technique validated in the Applications Information section.
Is the exposed pad (Pin 11) of the LTC3407EDD-3#PBF electrically connected, and how must it be handled on the PCB?
Yes, the exposed pad (Pin 11) of the LTC3407EDD-3#PBF is electrically connected to PGND and must be soldered directly to the PCB's power ground plane. Per the PIN CONFIGURATION diagram, it serves as the primary thermal and electrical return path for both switch currents - failure to connect it results in excessive junction temperature and potential device failure.
LTC3407EDD-3#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Fixed
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 3.3V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 1.8V, 3.3V
- Voltage - Output (Max):
- -
- Current - Output:
- 800mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
LTC3407EDD-3#PBF FAQ
1.How can I place an order for LTC3407EDD-3#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3407EDD-3#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3407EDD-3#PBF reliable?
The price and inventory of LTC3407EDD-3#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3407EDD-3#PBF is usually 5 days.
3.What payment methods are accepted for LTC3407EDD-3#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3407EDD-3#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3407EDD-3#PBF?
LTC3407EDD-3#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3407EDD-3#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3407EDD-3#PBF?
For technical support, including LTC3407EDD-3#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3407EDD-3#PBF requirements.
6.How does Aetrix verify that LTC3407EDD-3#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3407EDD-3#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3407EDD-3#PBF meets industry standards.
7.What is the process for return or replacement of LTC3407EDD-3#PBF?
All LTC3407EDD-3#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3407EDD-3#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3407EDD-3#PBF part is unused and in its original packaging.
Return procedure for LTC3407EDD-3#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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