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Analog Devices Inc. LTC3450EUD#PBF
- Part No.:
- LTC3450EUD#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
LTC3450EUD#PBF.pdf
- Description:
- IC REG CONV TFT LCD 3OUT 16QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,775
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Product details
Overview
LTC3450EUD#PBF from Analog Devices (formerly Linear Technology) is a triple-output TFT-LCD power supply IC integrating a synchronous boost converter and three charge pumps. It delivers 5.1V/10mA, ±10V or ±15V/500µA, and 15V/500µA from 1.5V–4.6V input, with >90% efficiency, <5mVP-P output ripple, and internal power-up sequencing for LCD panel initialization in handheld color displays.
For engineers reviewing the LTC3450EUD#PBF datasheet, LTC3450EUD#PBF pinout, LTC3450EUD#PBF application, or LTC3450EUD#PBF equivalent, key selection considerations include its 16-pin 3mm × 3mm QFN package, controlled AVDD/VGL/VGH turn-on sequence, MODE-driven blank/scan mode switching, and active discharge during shutdown - all critical for low-power, space-constrained TFT-LCD biasing.
Technical Context
The LTC3450EUD#PBF employs a fixed-frequency (550kHz nominal), current-mode synchronous boost regulator to generate 5.1V from 1.5V–4.6V input, with soft-start and inrush limiting. Its three independent charge pumps - doubler (V2X), tripler (V3X), and inverter (VNEG) - operate at 1/8 the boost frequency (62.5kHz) and are synchronized to minimize noise coupling.
Output sequencing is fully internal: AVDD reaches ~90% before enabling V2X; VNEG starts after AVDD stabilization; V3X enables only after VNEG crosses –5V (with ~4ms delay). The SHDN pin reduces quiescent current to <2µA and actively discharges all outputs, while MODE selects between high-efficiency scan mode (75µA VIN IQ) and ultra-low-power blank mode (30µA VIN IQ).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 1.5V to 4.6V - supports single Li-ion, 2–3 alkaline cells, or wide-input portable sources without external regulation. |
| AVDD Output | 5.100V ±1.0% at 10mA - precision-regulated main supply for TFT gate driver logic (AVDD). |
| V3X Output | 15.2V ±3.2% at 500µA - stable high-voltage source for positive gate drive (VGH) in small TFT panels. |
| VNEG Output | –10.1V ±3.2% at 500µA - negative rail for gate off-voltage (VGL), configurable to –5V or –15V via VINV connection. |
| Efficiency (AVDD) | >90% at 5mA load - minimizes thermal impact and extends battery life in compact handhelds. |
| Output Ripple (AVDD) | <5mVP-P - ensures clean biasing for sensitive analog pixel drivers and avoids display artifacts. |
| Quiescent Current (Scan) | 75µA typical at VIN - enables multi-day standby in PDA/handheld instrument applications. |
| Shutdown Current | <2µA - guarantees rapid, complete power-down of LCD panel with no residual leakage paths. |
Pinout & Package
Package: 16-lead (3mm × 3mm) plastic QFN with 0.75mm profile and exposed pad soldered to VNEG (Pin 3) - optimized for minimal PCB footprint and thermal performance in thin portable devices.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| C3+ (1) | Inverter flying capacitor positive node | AC-coupled node switching between GND and VINV; requires ≥10nF X5R ceramic for stable –5V/–10V generation. |
| C3– (2) | Inverter flying capacitor negative node | AC-coupled node switching between GND and VNEG; defines charge transfer path for negative rail synthesis. |
| VNEG (3) | Negative output terminal | Delivers –5V or –10V (configurable); exposed pad must be connected to this pin - not GND - for thermal and functional integrity. |
| MODE (4) | Power mode control input | High = scan mode (550kHz, full output capability); low = blank mode (15.6kHz, reduced IQ and output current). |
| SHDN (5) | Master shutdown input | Active-low; pulls all outputs to GND via internal discharge FETs and cuts total supply current to <2µA. |
| VIN (6) | Main input supply | Accepts 1.5V–4.6V; bypassed with 2.2µF X5R capacitor to sustain transient loads and reduce EMI. |
| VOUT (7) | Boost regulator output | 5.1V regulated rail feeding V2X/V3X charge pumps; requires 2.2–10µF low-ESR ceramic filtering. |
| SW (8) | Boost switch node | Connects to inductor; internal P-channel sync rectifier prevents reverse inductor current and reduces losses. |
| GND (9) | Signal and power ground | Common reference for all circuits; requires short, low-inductance PCB trace to all output capacitors. |
| C1– (10) | Doubler flying capacitor negative node | Switches between GND and VOUT; forms voltage-doubling stage generating 10.2V (V2X) nominal. |
| C1+ (11) | Doubler flying capacitor positive node | Switches between VOUT and V2X; completes charge transfer cycle for 2× multiplication. |
| V2X (12) | Doubler output | 10.2V at no load, rated for 500µA; powers auxiliary circuitry or serves as VINV for –10V generation. |
| C2– (13) | Tripler flying capacitor negative node | Switches between GND and VOUT; initiates 3× multiplication chain for 15.3V (V3X) output. |
| C2+ (14) | Tripler flying capacitor positive node | Switches between V2X and V3X; enables efficient 3× voltage gain using shared flying capacitor topology. |
| V3X (15) | Tripler output | 15.3V at no load, rated for 500µA; supplies high-side gate drive (VGH) in active-matrix TFT displays. |
| VINV (16) | Inverter positive input | Defines VNEG polarity and magnitude: tied to VOUT → –5V; tied to V2X → –10V; external diodes enable –15V. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated triple-output architecture | Eliminates need for three discrete DC/DC converters - reduces BOM count, layout area, and design validation effort. |
| Controlled power-up sequencing (AVDD → V2X → VNEG → V3X) | Prevents latch-up and electrostatic damage during LCD panel startup by enforcing safe voltage ramp order. |
| Active output discharge on shutdown | Ensures rapid, deterministic LCD turn-off without external bleed resistors or timing-critical external circuitry. |
| Blank/scan mode switching via MODE pin | Reduces system power by >50% during display idle periods while maintaining output regulation - critical for battery runtime. |
| Low-noise fixed-frequency operation | Enables predictable EMI filtering and avoids audible noise in audio-sensitive handheld environments. |
| 1mm maximum component profile solution | Meets mechanical constraints of ultra-thin cellular handsets and PDAs where Z-height is tightly budgeted. |
Applications
| Cellular Handsets with Color Display | Handheld Instruments |
|---|---|
|
Use Scenario: Powering 2.2″–3.5″ active-matrix TFT-LCDs in GSM/UMTS feature phones with single Li-ion battery. IC Role / Device Role / Timing Role: Generates AVDD (5.1V), VGH (15V), and VGL (–10V) with precise sequencing to initialize pixel transistors and prevent gate oxide stress. Use Value: Enables full-color display operation from 3.6V nominal battery while maintaining <5mVP-P ripple to avoid screen flicker or ghosting. |
Use Scenario: Biasing segmented or dot-matrix LCDs in portable multimeters, gas detectors, and medical monitors. IC Role / Device Role / Timing Role: Provides isolated, low-noise analog rails for LCD segment drivers and reference buffers during measurement cycles. Use Value: Delivers stable –10V and +15V from 2–3 alkaline cells with <2µA shutdown current - extending shelf life and field service intervals. |
| PDA Display Power | TFT-LCD Evaluation Platforms |
|
Use Scenario: Supplying 4.3″ WVGA TFT panels in Windows Mobile or Palm OS PDAs with dynamic backlight control. IC Role / Device Role / Timing Role: Synchronizes VGL/VGH ramp rates to match display controller timing, preventing vertical banding during wake-from-sleep transitions. Use Value: Achieves >90% efficiency across 1.5V–4.6V input range - sustaining display brightness over full battery discharge curve. |
Use Scenario: Reference power solution on manufacturer-provided evaluation boards for TFT-LCD module integration testing. IC Role / Device Role / Timing Role: Demonstrates compliant power sequencing, MODE-driven power state transitions, and SHDN-controlled fast turn-off per JEDEC JESD22-A108. Use Value: Accelerates customer design-in by validating layout, capacitor selection, and startup behavior against production-grade silicon. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar TFT-LCD power supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3407EDHC#PBF | Single 5.1V boost output only; no integrated charge pumps - requires external VGH/VGL generators. | Suitable only when external charge pump ICs or discrete solutions are acceptable for negative/high-voltage rails. | Select if board space allows separate bias ICs and design flexibility is prioritized over integration. |
| LTC3407-2EDHC#PBF | Dual-output version (5.1V + adjustable 3–30V); lacks negative rail generation and internal sequencing logic. | Applicable for simpler monochrome or STN LCDs requiring only positive bias, not full TFT triple-rail support. | Choose when VGL is grounded or generated externally, and sequencing is managed by host processor GPIO. |
Compared with LTC3450EUD#PBF, both alternatives require additional components to replicate its triple-rail, sequenced, and actively discharged functionality - increasing BOM cost, layout complexity, and validation time for TFT-LCD designs.
Availability
LTC3450EUD#PBF is available at Aetrix Electronics and suitable for cellular handsets with color display, handheld instruments, PDA display power, and TFT-LCD evaluation platforms requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.
Supply support for LTC3450EUD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance analog and power management portfolio with rigorous quality and longevity commitments.
The LTC3450EUD#PBF belongs to Linear's TFT-LCD power management IC family, designed specifically to replace discrete boost + charge pump solutions in space- and power-constrained portable displays.
FAQ
What is the absolute maximum input voltage rating for the LTC3450EUD#PBF?
The LTC3450EUD#PBF has an absolute maximum VIN rating of 7V, as specified in the Absolute Maximum Ratings table. Operation above 4.6V violates recommended conditions and may cause permanent damage or parametric shift. The device is designed for 1.5V–4.6V operation - compatible with single Li-ion (2.7–4.2V) or 2–3 alkaline cells (3–4.5V).
Can the LTC3450EUD#PBF generate –15V on VNEG, and what external components are required?
Yes, the LTC3450EUD#PBF can generate –15V on VNEG using two external low-current Schottky diodes, as shown in Figure TA02 of the datasheet. VINV must be connected to V3X (15V), and diodes steer charge to extend inversion range. This configuration delivers –15V/500µA and is validated in the typical application circuit - no change to the LTC3450EUD#PBF itself is needed.
How does the MODE pin affect efficiency and output current capability of the LTC3450EUD#PBF?
When MODE = GND, the LTC3450EUD#PBF enters blank mode: boost switching frequency drops from 550kHz to 15.62kHz, reducing switching losses and cutting VIN quiescent current to 30µA (typ). However, VOUT max current falls to ~3mA, and V2X/V3X/VNEG output current capability is proportionally reduced - making it ideal for display idle states where power savings outweigh drive strength.
Is the exposed pad on the LTC3450EUD#PBF electrically connected, and how must it be handled on the PCB?
Yes, the exposed pad on the LTC3450EUD#PBF is electrically connected to Pin 3 (VNEG) - not GND - and must be soldered directly to a PCB copper area tied to VNEG. Connecting it to GND violates the internal electrical structure and will impair negative rail regulation and thermal performance. The datasheet explicitly warns: "DO NOT CONNECT EXPOSED PAD TO GROUND."
What is the purpose of the VNEG-to-V3X delay, and how is it implemented internally in the LTC3450EUD#PBF?
The VNEG-to-V3X delay (~4ms nominal) in the LTC3450EUD#PBF ensures VGL reaches sufficient negative voltage before VGH rises, preventing pixel transistor damage during LCD power-up. It is implemented via an internal timer triggered when VNEG crosses –5V; only then does the tripler stage enable. This sequencing is hardwired and requires no external components or host intervention.
LTC3450EUD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Converter, TFT LCD
- Voltage - Input:
- 1.5V ~ 4.6V
- Number of Outputs:
- 3
- Voltage - Output:
- 5.1V, -5V, ±10V, ±15V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (3x3)
LTC3450EUD#PBF FAQ
1.How can I place an order for LTC3450EUD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3450EUD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3450EUD#PBF reliable?
The price and inventory of LTC3450EUD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3450EUD#PBF is usually 5 days.
3.What payment methods are accepted for LTC3450EUD#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3450EUD#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3450EUD#PBF?
LTC3450EUD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3450EUD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3450EUD#PBF?
For technical support, including LTC3450EUD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3450EUD#PBF requirements.
6.How does Aetrix verify that LTC3450EUD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3450EUD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3450EUD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3450EUD#PBF?
All LTC3450EUD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3450EUD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3450EUD#PBF part is unused and in its original packaging.
Return procedure for LTC3450EUD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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