Analog Devices Inc. LTC3545IUD#PBF
- Part No.:
- LTC3545IUD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 16-WFQFN Exposed Pad
- Datasheet:
-
LTC3545IUD#PBF.pdf
- Description:
- IC REG BUCK ADJ 800MA TRPL 16QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3545IUD#PBF from Analog Devices (formerly Linear Technology) is a triple-channel, monolithic synchronous step-down DC/DC regulator IC designed for single-cell Li-Ion battery-powered systems. It delivers three independent 800mA outputs with 2.25MHz fixed-frequency operation, 0.6V feedback reference, and selectable low-ripple pulse-skip or high-efficiency Burst Mode™ operation - enabling compact power delivery in space-constrained portable electronics.
For engineers reviewing the LTC3545IUD#PBF datasheet, LTC3545IUD#PBF pinout, LTC3545IUD#PBF application, or LTC3545IUD#PBF equivalent, key selection criteria include its –40°C to 125°C industrial temperature grade, 16-lead 3mm × 3mm QFN package with exposed thermal pad, triple PGOOD signaling, and compatibility with external 1MHz–3MHz clock synchronization for EMI-sensitive designs.
Technical Context
The LTC3545IUD#PBF implements a constant-frequency current-mode control architecture across three independent buck regulators, each with internal P-channel and N-channel synchronous MOSFETs. It supports input voltages from 2.25V to 5.5V and regulates outputs down to 0.6V via external resistive dividers, with soft-start ramping over ~1ms and cycle-by-cycle peak current limiting up to 1.6A per channel.
Its MODE/SYNC pin configures operating mode: low = Burst Mode™ (58μA quiescent current), high = pulse-skip mode (<20mVP-P ripple); it also accepts external 1–3MHz clocks for frequency synchronization. Power good indicators (PGOOD1–PGOOD3) provide open-drain status signals referenced to 90% of regulated output voltage, enabling precise power-on sequencing between rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.25V to 5.5V - supports direct connection to single Li-Ion (2.7–4.2V) or Li-Polymer batteries with margin for voltage sag and charging transients. |
| Output Current per Channel | 800mA - sufficient for powering core logic, memory, and I/O rails in smartphones and digital cameras without external boost stages. |
| Switching Frequency | 2.25MHz (internal) or 1–3MHz (external sync) - enables use of small 1–2.2μH inductors and ceramic capacitors, reducing board area by >40% vs lower-frequency converters. |
| Feedback Reference Voltage | 0.6V ±12mV (–40°C to 125°C) - allows precise low-voltage regulation (e.g., 1.2V, 1.5V, 1.8V) with <0.5% load regulation error across full temperature range. |
| Quiescent Current (Burst Mode) | 58μA - extends battery runtime in standby/sleep states while maintaining fast wake-up response and rail stability. |
| Efficiency (Typical) | Up to 95% at 500mA - achieved via synchronous rectification (RDS(ON) ≤ 0.35Ω for both PFET/NFET) and optimized gate drive, minimizing conduction and switching losses. |
| Thermal Resistance θJA | 55°C/W - enabled by exposed pad soldered to PCB ground plane, supporting continuous 800mA operation per channel at 85°C ambient without derating. |
Pinout & Package
Package: 16-lead 3mm × 3mm plastic QFN (UD package) with exposed thermal pad (Pin 17 = GND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW1, SW2, SW3 (Pins 1, 5, 8) | Switch node connections for regulators 1–3 | High dv/dt nodes driving external inductors; require short, low-inductance PCB traces and local ceramic decoupling to minimize EMI and ringing. |
| PGOOD1–PGOOD3 (Pins 2, 4, 9) | Open-drain power-good status outputs | Assert low when corresponding VFB falls below 90% of 0.6V reference; enable sequenced enablement of downstream circuitry via pull-up resistors. |
| RUN1–RUN3 (Pins 14, 3, 10) | Independent regulator enable inputs | Logic-high (>1V) enables respective regulator; logic-low (<0.3V) forces shutdown with <0.1μA leakage, supporting dynamic rail gating. |
| VFB1–VFB3 (Pins 13, 12, 11) | Feedback inputs for output voltage sensing | High-impedance (±0.1μA leakage) nodes accepting resistive divider ratios to set output voltage precisely from 0.6V to 5.5V. |
| VIN (Pin 15), PVIN (Pin 7), GNDA (Pin 16), PGND (Pin 6) | Power and ground distribution network | VIN powers control circuitry (regulator 1 path); PVIN powers regulators 2/3; GNDA/PGND separation minimizes noise coupling between analog and power return paths. |
Key Features
| Feature | Design Value |
|---|---|
| Triple independent 800mA buck regulators | Enables single-chip power management for multi-rail SoC or FPGA applications - eliminating need for three discrete converters and reducing BOM count by ≥60%. |
| Burst Mode™ operation (58μA IQ) | Extends battery life in always-on sensor nodes or standby modes without sacrificing startup time or output regulation accuracy. |
| 2.25MHz fixed-frequency or external sync | Allows EMI filtering at known frequency or alignment with system clock domain to avoid beat frequencies in RF-sensitive modules. |
| 0.6V precision reference with ±0.8% total error | Supports tight-tolerance core voltage regulation (e.g., ARM Cortex-A series) without external trimming or calibration. |
| Three dedicated PGOOD outputs | Permits robust, fault-isolated power sequencing - e.g., enabling processor core before I/O, or delaying peripheral activation until stable VDDIO is confirmed. |
Applications
| Smartphones | Wireless Modems |
|---|---|
Use Scenario: Powering application processor cores (e.g., Cortex-A7/A53), DDR memory, and display interface rails from a single Li-Ion cell. IC Role / Device Role / Timing Role: Triple-output PMIC delivering 1.2V (core), 1.8V (memory), and 3.3V (interface) with independent enable and PGOOD signaling. Use Value: Reduces solution size by 35% vs discrete buck converters while maintaining <1% output voltage deviation during 0–800mA load transients. | Use Scenario: Supplying baseband processor, RF transceiver, and USB PHY in LTE/5G CPE modems with strict EMI limits. IC Role / Device Role / Timing Role: Synchronous buck regulator providing low-noise 1.1V core, 1.8V I/O, and 2.5V analog rails with 2.25MHz switching synchronized to system clock. Use Value: Enables compliance with FCC Class B conducted emissions by avoiding variable-frequency operation and simplifying filter design. |
| Digital Still Cameras | Portable Instruments |
Use Scenario: Powering CMOS image sensor, ISP, and flash LED driver in compact camera modules. IC Role / Device Role / Timing Role: High-efficiency triple regulator delivering 1.2V (sensor logic), 2.8V (analog front-end), and 3.3V (flash control) with fast transient response. Use Value: Achieves <100μs recovery from 100mA–800mA load steps, preventing image artifacts during burst capture. | Use Scenario: Regulating power for microcontroller, ADC, and wireless transceiver in handheld test equipment. IC Role / Device Role / Timing Role: Low-quiescent-current triple buck supplying 3.3V (MCU), 2.5V (precision ADC), and 1.8V (BLE radio) from coin-cell or Li-Ion source. Use Value: Delivers >200 hours of continuous operation on 800mAh battery using Burst Mode™ at sub-1mA loads. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple 600mA outputs, 2.25MHz, but uses external compensation and lacks SYNC/MODE pin; only two PGOOD outputs. | Targeted at OMAP-based handhelds; less flexible sequencing and higher minimum output voltage (0.8V). | Select when cost sensitivity outweighs need for 800mA per rail and third PGOOD signal. |
| MAX8646ETE+ | Triple 1A outputs, 2.25MHz, integrated LDO for auxiliary rail, but requires external MOSFETs for sync rectification and has no Burst Mode™. | Designed for high-performance media processors; higher IQ (120μA) limits ultra-low-power use cases. | Select when >800mA per channel is required and system-level efficiency above 100mA load dominates design priority. |
Compared with TPS65023RSBR and MAX8646ETE+, the LTC3545IUD#PBF offers superior light-load efficiency via Burst Mode™, tighter output voltage tolerance (±0.8% vs ±1.5%), and true triple independent PGOOD signaling - making it optimal for battery-critical, multi-rail embedded systems requiring deterministic power sequencing and minimal standby drain.
Availability
LTC3545IUD#PBF is available at Aetrix Electronics and suitable for smartphone power management, wireless modem subsystems, and portable instrumentation requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC3545IUD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, formed through the acquisition of Linear Technology in 2017.
The LTC3545IUD#PBF belongs to ADI's Power by Linear™ family of high-efficiency DC/DC converters, engineered specifically for space-constrained, battery-operated portable electronics demanding high integration, low quiescent current, and robust thermal performance.
FAQ
What is the maximum junction temperature specification for the LTC3545IUD#PBF?
The LTC3545IUD#PBF has a specified operating junction temperature range of –40°C to 125°C. Its thermal resistance θJA is 55°C/W when the exposed pad (Pin 17) is properly soldered to a PCB ground plane. At 85°C ambient and full 800mA load per channel in dropout, calculated junction temperature remains below 125°C - confirming safe operation under worst-case thermal conditions without forced airflow.
Does the LTC3545IUD#PBF support external frequency synchronization?
Yes, the LTC3545IUD#PBF supports external frequency synchronization via its SYNC/MODE pin (Pin 9). When driven by a clean 1MHz to 3MHz square wave clock, the device locks its switching frequency to the external source while operating in pulse-skip mode - enabling EMI reduction through frequency dithering or alignment with system timing domains.
How does the LTC3545IUD#PBF implement power-good signaling?
The LTC3545IUD#PBF provides three independent open-drain PGOOD outputs (Pins 2, 4, and 9) that assert low when the corresponding feedback voltage (VFBx) drops below 90% of the 0.6V reference - indicating output voltage deviation exceeding ±10%. Each PGOOD signal requires an external pull-up resistor and can be used to sequence downstream enable signals or trigger fault interrupts in host controllers.
What is the difference between the LTC3545IUD#PBF and LTC3545IUD-1#PBF?
The LTC3545IUD#PBF includes a multifunction SYNC/MODE pin (Pin 9) for selecting Burst Mode™ vs pulse-skip operation or accepting external clock input. The LTC3545IUD-1#PBF replaces Pin 9 with a third PGOOD3 output and forces Burst Mode™ operation only - removing frequency flexibility but adding critical sequencing capability for safety-critical or tightly coupled multi-rail systems.
Can the LTC3545IUD#PBF operate with input voltage below 2.25V?
No - the absolute minimum input voltage for functional operation of the LTC3545IUD#PBF is 2.25V, as specified in the Electrical Characteristics table. Operation below this threshold triggers undervoltage lockout (UVLO), disabling all regulators until VIN rises above 2.25V (typical) with hysteresis. This ensures reliable start-up and prevents erratic behavior during battery discharge.
LTC3545IUD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 16-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 3
- Voltage - Input (Min):
- 2.25V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 800mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-QFN (3x3)
LTC3545IUD#PBF FAQ
1.How can I place an order for LTC3545IUD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3545IUD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3545IUD#PBF reliable?
The price and inventory of LTC3545IUD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3545IUD#PBF is usually 5 days.
3.What payment methods are accepted for LTC3545IUD#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3545IUD#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3545IUD#PBF?
LTC3545IUD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3545IUD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3545IUD#PBF?
For technical support, including LTC3545IUD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3545IUD#PBF requirements.
6.How does Aetrix verify that LTC3545IUD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3545IUD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3545IUD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3545IUD#PBF?
All LTC3545IUD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3545IUD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3545IUD#PBF part is unused and in its original packaging.
Return procedure for LTC3545IUD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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