Analog Devices Inc. LTC3548AEDD#PBF
- Part No.:
- LTC3548AEDD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC3548AEDD#PBF.pdf
- Description:
- IC REG BUCK BOOST ADJ DL 10DFN
- Quantity:
- Payment:

- Shipping:

Inventory:203
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Product details
Overview
LTC3548AEDD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel synchronous step-down DC/DC regulator with integrated 0.35Ω P-channel and 0.30Ω N-channel MOSFETs, delivering 400mA on Channel 2 and 800mA on Channel 1 across 2.5V–5.5V input. It operates at a fixed 2.25MHz switching frequency, supports adjustable output voltages from 0.6V to 5V per channel, and features Burst Mode® operation for 40μA quiescent current - ideal for battery-powered portable electronics requiring compact power conversion.
For engineers reviewing the LTC3548AEDD#PBF datasheet, LTC3548AEDD#PBF pinout, LTC3548AEDD#PBF application, or LTC3548AEDD#PBF equivalent, key selection considerations include its dual-output 2.25MHz constant-frequency architecture, user-selectable Burst Mode® vs pulse-skipping mode, 100% duty-cycle dropout operation, Power-On Reset (POR) output, and external synchronization capability via MODE/SYNC pin.
Technical Context
The LTC3548AEDD#PBF employs a current-mode control architecture with shared 2.25MHz oscillator and in-phase dual-channel operation. Each channel uses internal P-channel high-side and N-channel low-side synchronous switches, eliminating external Schottky diodes while enabling >95% peak efficiency and ±8.5% POR threshold accuracy.
Its MODE/SYNC pin serves triple function: selecting Burst Mode® (low IQ) or pulse-skipping (low ripple), enabling external clock synchronization, and forcing pulse-skipping during sync. The device enters 100% duty-cycle dropout when VIN approaches VOUT, with RDS(ON) increasing at lower VIN - requiring thermal validation under low-input, high-load conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 5.5V - supports single-cell Li-ion, Li-polymer, and 3.3V/5V rail inputs without pre-regulation. |
| Switching Frequency | 2.25MHz (typ) - enables use of sub-3mm-height inductors and 10μF ceramic capacitors for ultra-compact layouts. |
| Output Current Capability | Channel 1: 800mA; Channel 2: 400mA - defined by peak switch current limits of 1.2A and 0.7A respectively. |
| Feedback Reference Voltage | 0.600V (±2%) - sets output voltage via external resistor divider; enables 0.6V–5V adjustment range. |
| Quiescent Current | 40μA (Burst Mode®, both channels active) - extends battery runtime in standby/sleep states. |
| Shutdown Current | <1μA - ensures negligible drain during system off-state. |
| Power-On Reset Threshold | ±8.5% of regulated output - provides reliable system reset signaling when either output deviates beyond tolerance. |
Pinout & Package
Package: 10-lead (3mm × 3mm) plastic DFN with exposed thermal pad (Pin 11 = PGND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VFB1 (Pin 1) | Channel 1 feedback input | Connects to resistor divider midpoint; regulates VOUT1 to 0.6V reference - determines output voltage setting. |
| RUN/SS1 (Pin 2) | Channel 1 enable & soft-start | High = enable; low = shutdown; RC network here controls startup slew rate and inrush limiting. |
| VIN (Pin 3) | Main power input | Supplies both regulators; requires local 10μF ceramic decoupling directly at pin for EMI suppression. |
| SW1 (Pin 4) | Channel 1 switch node | Connects to inductor; swings between VIN and GND - critical high-dI/dt node requiring short, wide trace routing. |
| NC (Pin 5) | No connect | Internally unconnected; recommended to tie to GND on PCB for shielding and thermal conduction. |
| MODE/SYNC (Pin 6) | Mode control & sync input | Logic level selects Burst Mode® (VIN) or pulse-skipping (GND); accepts external 2.25MHz clock for synchronization. |
| SW2 (Pin 7) | Channel 2 switch node | Identical function to SW1 but for second regulator - must be routed separately to avoid cross-coupling. |
| POR (Pin 8) | Power-On Reset open-drain output | Pulled low if either output is out-of-regulation; releases after 65,536 clock cycles (~29ms in pulse-skipping mode). |
| RUN/SS2 (Pin 9) | Channel 2 enable & soft-start | Independent control of Channel 2; allows staggered startup or selective shutdown of second output. |
| VFB2 (Pin 10) | Channel 2 feedback input | Same function as VFB1 but for VOUT2 - enables independent voltage programming per channel. |
Key Features
| Feature | Design Value |
|---|---|
| Dual synchronous buck topology | Eliminates external Schottky diodes; achieves >95% efficiency at medium loads with integrated 0.35Ω/0.30Ω MOSFETs. |
| User-selectable light-load mode | Burst Mode® reduces IQ to 40μA; pulse-skipping maintains 2.25MHz operation for lowest output ripple (<35mVP-P). |
| 100% duty-cycle dropout | P-channel high-side switch remains fully on when VIN ≈ VOUT - sustains regulation down to input voltages near output level. |
| External frequency synchronization | MODE/SYNC pin accepts 2.25MHz external clock - enables noise-sensitive systems to avoid beat frequencies or align switching with other converters. |
| Integrated Power-On Reset (POR) | Single open-drain output asserts low until both outputs stabilize within ±8.5%; eliminates need for external supervisor IC. |
Applications
| PDAs / Palmtop PCs | Digital Cameras |
|---|---|
Use Scenario: Powering core logic (1.8V) and I/O (2.5V) rails from single Li-ion cell in handheld computing devices. IC Role / Device Role / Timing Role: Dual-output DC/DC regulator providing tightly regulated, sequenced, and low-noise supplies for CPU, memory, and display interface. Use Value: 2.25MHz operation enables <3mm-height inductors and small ceramic caps - meeting strict height constraints in ultra-thin form factors. |
Use Scenario: Supplying image sensor (2.8V), processor (1.2V), and memory (3.3V) from 3.7V battery in compact digital cameras. IC Role / Device Role / Timing Role: Dual synchronous buck converter generating two independent, adjustable, and low-ripple power rails with coordinated soft-start. Use Value: Burst Mode® extends battery life during viewfinder standby; POR output triggers camera boot sequence only after stable power-up. |
| Cellular Phones | Wireless Modems |
Use Scenario: Delivering RF transceiver (2.5V) and baseband processor (1.8V) supplies in GSM/UMTS handsets with aggressive size targets. IC Role / Device Role / Timing Role: Dual-channel step-down regulator with independent RUN/SS pins enabling dynamic power gating of subsystems. Use Value: 40μA quiescent current minimizes self-discharge during deep sleep; 100% duty-cycle operation maintains regulation during battery sag. |
Use Scenario: Generating 3.3V and 1.8V rails for Wi-Fi/Bluetooth SoC and Ethernet PHY in residential DSL/wireless modems. IC Role / Device Role / Timing Role: Synchronized dual buck converter allowing phase-aligned switching to reduce input ripple and EMI filter size. Use Value: MODE/SYNC pin enables synchronization to system clock - simplifying EMI compliance testing and reducing conducted emissions peaks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62130ARGTR | Single-output 3A buck; no dual-channel integration; 2.5MHz fixed frequency; 17μA IQ in DCS-Control™ mode. | Requires two separate ICs to replicate dual-rail functionality; lacks POR and MODE/SYNC flexibility. | Choose when higher per-rail current (>800mA) or lower IQ is prioritized over integration and feature set. |
| MAX17504ATP+T | Dual-output, but asynchronous (external diode required); 400kHz–2.2MHz programmable frequency; 100μA IQ in skip mode. | Higher board area due to external diodes; lower switching frequency demands larger magnetics; no integrated POR. | Prefer when cost sensitivity outweighs size/efficiency trade-offs and external diode placement is acceptable. |
Compared with TPS62130ARGTR and MAX17504ATP+T, the LTC3548AEDD#PBF delivers true dual-channel integration with synchronous rectification, integrated POR, and selectable light-load modes - offering superior space efficiency, lower EMI, and simplified BOM for compact, battery-operated dual-rail systems.
Availability
LTC3548AEDD#PBF is available at Aetrix Electronics and suitable for PDAs/palmtop PCs, digital cameras, cellular phones, wireless modems, and DSL modems requiring stable component supply with guaranteed long-term manufacturability.
Supply support for LTC3548AEDD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and continues its legacy of high-performance analog, power management, and precision signal conditioning ICs.
The LTC3548AEDD#PBF belongs to Linear's µPower synchronous buck regulator product line, designed specifically for space-constrained, battery-powered portable electronics demanding high efficiency, low quiescent current, and minimal external components.
FAQ
What is the maximum output current supported by each channel of the LTC3548AEDD#PBF?
The LTC3548AEDD#PBF supports up to 800mA on Channel 1 and 400mA on Channel 2, determined by internal peak switch current limits of 1.2A and 0.7A respectively. These values assume proper thermal design, appropriate inductor selection (e.g., 4.7μH for Channel 1), and operation within the 2.5V–5.5V input range. Derating is required at elevated ambient temperatures or high duty cycles.
How does the MODE/SYNC pin affect the operation of the LTC3548AEDD#PBF?
The MODE/SYNC pin on the LTC3548AEDD#PBF controls three functions: tying it to VIN enables Burst Mode® for lowest quiescent current (40μA), tying it to GND selects pulse-skipping mode for lowest output ripple (<35mVP-P), and applying an external 2.25MHz clock synchronizes switching while automatically selecting pulse-skipping. The pin must never be left floating.
Can the LTC3548AEDD#PBF operate in dropout, and what happens to efficiency?
Yes, the LTC3548AEDD#PBF supports 100% duty-cycle dropout operation: when VIN drops near VOUT, the P-channel high-side switch remains continuously on. Efficiency declines in dropout due to increased RDS(ON) of the P-MOSFET at low VIN - datasheet shows RDS(ON) rising from ~0.35Ω at 3.6V to >0.45Ω at 2.7V, increasing conduction loss. Thermal design must account for this.
What is the purpose and behavior of the POR pin on the LTC3548AEDD#PBF?
The POR (Power-On Reset) pin on the LTC3548AEDD#PBF is an open-drain output that pulls low whenever either output voltage deviates by more than ±8.5% from its target. It releases (goes high-impedance) only after both outputs remain in regulation for 65,536 oscillator cycles (~29ms in pulse-skipping mode). During Burst Mode® light loads, delay increases significantly due to intermittent clocking.
Does the LTC3548AEDD#PBF require external compensation components?
No, the LTC3548AEDD#PBF features internally compensated current-mode control - no external compensation network is needed for stable operation with standard output capacitor types (e.g., ceramic, tantalum, polymer). However, feedforward capacitors (CF) across the upper feedback resistor are optional to improve transient response, and layout best practices (short FB traces, ground plane under exposed pad) remain critical.
LTC3548AEDD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down, Step-Up/Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck, Buck-Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5V
- Current - Output:
- 400mA, 800mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
LTC3548AEDD#PBF FAQ
1.How can I place an order for LTC3548AEDD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3548AEDD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3548AEDD#PBF reliable?
The price and inventory of LTC3548AEDD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3548AEDD#PBF is usually 5 days.
3.What payment methods are accepted for LTC3548AEDD#PBF?
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LTC3548AEDD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3548AEDD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3548AEDD#PBF?
For technical support, including LTC3548AEDD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3548AEDD#PBF requirements.
6.How does Aetrix verify that LTC3548AEDD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3548AEDD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3548AEDD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3548AEDD#PBF?
All LTC3548AEDD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3548AEDD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3548AEDD#PBF part is unused and in its original packaging.
Return procedure for LTC3548AEDD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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