Analog Devices Inc. LTC3548AIDD#PBF
- Part No.:
- LTC3548AIDD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC3548AIDD#PBF.pdf
- Description:
- IC REG BUCK BOOST ADJ DL 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3548AIDD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel synchronous step-down DC/DC regulator with independent 400mA and 800mA output capability, 2.25MHz fixed switching frequency, 2.5V–5.5V input range, and adjustable 0.6V–5V outputs - designed for space-constrained portable electronics requiring high efficiency and low quiescent current.
For engineers reviewing the LTC3548AIDD#PBF datasheet, LTC3548AIDD#PBF pinout, LTC3548AIDD#PBF application, or LTC3548AIDD#PBF equivalent, key selection considerations include its dual-output Burst Mode® vs pulse-skipping mode trade-off, 40μA total quiescent current in active operation, 100% duty-cycle dropout behavior, integrated 0.35Ω P-channel/0.30Ω N-channel synchronous switches, and 3mm × 3mm DFN-10 package with exposed thermal pad.
Technical Context
The LTC3548AIDD#PBF implements a constant-frequency current-mode control architecture with shared 2.25MHz oscillator across both channels, enabling precise phase alignment and simplified EMI filtering. Each channel features independent RUN/SS enable/soft-start inputs, feedback pins referenced to a trimmed 0.6V internal reference, and overvoltage/undervoltage detection feeding a common open-drain POR output.
Its MODE/SYNC pin serves dual functions: selecting between Burst Mode® (for peak light-load efficiency) or pulse-skipping mode (for lowest output ripple), and accepting external synchronization signals up to 2.25MHz. The device enters 100% duty-cycle dropout when VIN approaches VOUT, with RDS(ON) of the P-channel switch increasing at lower VIN - a critical thermal design factor confirmed in Figure G09 and G10.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 5.5V - supports single-cell Li-ion, Li-polymer, or dual-cell alkaline/NiMH battery inputs without pre-regulation. |
| Switching Frequency | 2.25MHz (typical) - enables use of sub-1mm-height inductors and 10μF ceramic capacitors, minimizing board area. |
| Output Current Capability | Channel 1: 400mA; Channel 2: 800mA - defined by peak switch current limits of 0.7A and 1.2A respectively. |
| Feedback Reference Voltage | 0.600V ±12mV (–40°C to 125°C) - sets output voltage via external resistor divider; enables 0.6V–5V adjustment range. |
| Quiescent Current | 40μA total (both channels active, Burst Mode®) - extends battery runtime in always-on subsystems like real-time clocks or sensors. |
| Shutdown Current | <1μA - ensures negligible battery drain during system sleep or storage. |
| Power-On Reset Threshold | ±8.5% output regulation window - asserts POR low until both outputs stabilize within tolerance for ≥216 clock cycles (~29ms). |
Pinout & Package
Package: 10-lead (3mm × 3mm) plastic DFN with exposed thermal pad (Pin 11 = PGND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VFB1 (Pin 1) | Channel 1 feedback input | Connects to resistive divider on VOUT1; regulates output by comparing to 0.6V reference. |
| RUN/SS1 (Pin 2) | Channel 1 enable & soft-start | Pull to VIN to enable; pull to GND to disable; RC network adds controlled startup ramp. |
| VIN (Pin 3) | Main power input | Supplies both regulators; requires local 10μF ceramic decoupling to PGND. |
| SW1 (Pin 4) | Channel 1 switch node | Connects to inductor; swings between VIN and GND; high di/dt node requiring short layout. |
| NC (Pin 5) | No connect | Internally unconnected; recommended to tie to GND for EMI shielding. |
| MODE/SYNC (Pin 6) | Mode selection & sync input | Tie to VIN for Burst Mode®; tie to GND for pulse-skipping; accept external 2.25MHz clock for synchronization. |
| SW2 (Pin 7) | Channel 2 switch node | Connects to inductor; identical function to SW1 but for second regulator channel. |
| POR (Pin 8) | Power-on reset output | Open-drain logic output pulled low if either VOUT is outside ±8.5%; releases after stabilization delay. |
| RUN/SS2 (Pin 9) | Channel 2 enable & soft-start | Independent control of second regulator; same functionality as RUN/SS1. |
| VFB2 (Pin 10) | Channel 2 feedback input | Connects to resistive divider on VOUT2; identical reference and regulation behavior as VFB1. |
| Exposed Pad (Pin 11) | Power ground (PGND) | Mandatory connection to PCB ground plane; primary thermal path and return for high-current switch paths. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent synchronous buck regulators | Eliminates need for external Schottky diodes; achieves up to 95% efficiency with integrated 0.35Ω P-channel and 0.30Ω N-channel MOSFETs. |
| User-selectable light-load operating mode | Burst Mode® reduces quiescent current to 40μA while maintaining regulation; pulse-skipping mode minimizes output ripple below 35mVP-P. |
| 100% duty-cycle dropout operation | Enables seamless transition to linear regulation when VIN drops near VOUT; critical for battery end-of-life support. |
| Externally synchronizable 2.25MHz oscillator | Allows noise-sensitive systems to lock switching frequency to a clean system clock, avoiding beat frequencies and easing EMI compliance. |
| Integrated power-on reset with programmable delay | POR output asserts low until both outputs settle within ±8.5%; delay scales with load-dependent burst frequency or fixed at ~29ms in pulse-skipping mode. |
Applications
| Mobile Baseband Power | Digital Camera Core Logic |
|---|---|
|
Use Scenario: Dual-rail power for cellular baseband processors requiring 1.8V core and 2.5V I/O rails from a single Li-ion cell. IC Role / Device Role / Timing Role: Primary dual-output DC/DC converter delivering regulated 1.8V/800mA and 2.5V/400mA with fast transient response to burst-mode RF transmission loads. Use Value: 2.25MHz switching allows compact 2.2μH/4.7μH inductors and 10μF ceramic caps; 40μA quiescent current extends standby time between calls. |
Use Scenario: Power management for digital camera SoCs with separate processor core, image sensor interface, and memory I/O domains. IC Role / Device Role / Timing Role: Dual synchronous buck supplying 1.2V processor core and 2.8V sensor interface, each independently enabled and soft-started. Use Value: Independent RUN/SS pins allow staggered power-up sequencing; POR output coordinates system reset with power rail stability. |
| Wireless Modem RF Front-End | PDA Application Processor |
|
Use Scenario: Compact power solution for DSL/wireless modems where board space is constrained and thermal dissipation is limited. IC Role / Device Role / Timing Role: High-efficiency dual regulator generating 1.5V RF amplifier bias and 3.3V digital logic supply from 3.6V nominal input. Use Value: 3mm × 3mm DFN package with exposed pad meets thermal requirements in sealed enclosures; Burst Mode® maintains >85% efficiency at 10mA loads. |
Use Scenario: Main power IC for palmtop PCs with ARM-based application processors and multiple peripheral voltage domains. IC Role / Device Role / Timing Role: Dual buck controller providing 1.0V CPU core and 1.8V DDR memory supply, with optional external soft-start for inrush current limiting. Use Value: Adjustable 0.6V–5V outputs accommodate evolving processor voltage requirements; MODE/SYNC pin enables system-level clock synchronization for deterministic EMI. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62130ARGTR | Single-output 3A buck; no dual-channel capability; 2.5MHz switching; 2.7V–6V input; 0.6V–5.5V output; 17μA IQ. | Requires two devices to match LTC3548AIDD#PBF's dual-rail functionality; lacks POR and independent RUN/SS control. | Choose when higher per-channel current (>800mA) is needed and board area permits two ICs; not suitable for space-constrained dual-rail designs. |
| MAX17504ATP+T | Dual-output 2A/2A buck; 200kHz–2.2MHz programmable frequency; 4.5V–36V input; 0.8V–15V output; 120μA IQ. | Higher input voltage range and output current, but larger 20-pin TQFN package; no Burst Mode®; higher quiescent current. | Prefer for industrial or automotive applications with wide input range; avoid for battery-powered portable devices needing ultra-low IQ. |
Compared with TPS62130ARGTR and MAX17504ATP+T, the LTC3548AIDD#PBF uniquely delivers tightly integrated dual outputs in a 3mm × 3mm footprint with industry-leading 40μA light-load IQ, dedicated POR signaling, and true 2.25MHz fixed-frequency operation - making it optimal for miniaturized, battery-sensitive consumer electronics.
Availability
LTC3548AIDD#PBF is available at Aetrix Electronics and suitable for mobile baseband power, digital camera core logic, wireless modem RF front-end, PDA application processor, and portable medical instrumentation requiring stable component supply across production lifecycles.
Supply support for LTC3548AIDD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, serving industrial, automotive, communications, and consumer markets.
The LTC3548AIDD#PBF belongs to Linear Technology's µPower DC/DC converter product line, engineered specifically for ultra-low-power portable electronics where battery life, board area, and light-load efficiency are critical design constraints.
FAQ
What is the maximum output current capability of each channel in the LTC3548AIDD#PBF?
The LTC3548AIDD#PBF provides 400mA on Channel 1 and 800mA on Channel 2, defined by peak switch current limits of 0.7A and 1.2A respectively. These values are verified across –40°C to 125°C and assume proper thermal management via the exposed PGND pad. Output current is also limited by inductor saturation current and thermal derating at elevated ambient temperatures.
How does the MODE/SYNC pin affect the operation of the LTC3548AIDD#PBF?
The MODE/SYNC pin on the LTC3548AIDD#PBF selects between Burst Mode® (tie to VIN) for highest light-load efficiency or pulse-skipping mode (tie to GND) for lowest output ripple. When driven by an external 2.25MHz clock, it forces pulse-skipping mode and synchronizes both channels' switching edges - essential for reducing beat frequencies in multi-rail systems.
Can the LTC3548AIDD#PBF operate with input voltages below 2.5V?
No - the LTC3548AIDD#PBF has a specified minimum input voltage of 2.5V per Absolute Maximum Ratings and Electrical Characteristics tables. Operation below 2.5V risks undervoltage lockout activation or unstable regulation. The device incorporates UVLO that disables switching when VIN falls below ~1.65V, preventing erratic behavior but not supporting sub-2.5V operation.
What is the purpose of the exposed pad (Pin 11) on the LTC3548AIDD#PBF DFN package?
The exposed pad (Pin 11) on the LTC3548AIDD#PBF is designated PGND - a dedicated power ground connection that serves as the primary thermal conduction path and low-impedance return for high-current switch node currents. It must be soldered to a solid PCB ground plane; failure to do so degrades thermal performance, increases RDS(ON) heating, and may cause premature thermal shutdown.
Does the LTC3548AIDD#PBF support independent voltage setting for each output?
Yes - the LTC3548AIDD#PBF supports fully independent output voltage programming via separate feedback dividers on VFB1 and VFB2. Each channel uses the same 0.6V internal reference, allowing individual outputs to be set anywhere from 0.6V to 5V using standard resistor calculations: VOUT = 0.6V × (1 + R2/R1). No coupling or interaction exists between the two regulation loops.
LTC3548AIDD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down, Step-Up/Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck, Buck-Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5V
- Current - Output:
- 400mA, 800mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
LTC3548AIDD#PBF FAQ
1.How can I place an order for LTC3548AIDD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3548AIDD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3548AIDD#PBF reliable?
The price and inventory of LTC3548AIDD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3548AIDD#PBF is usually 5 days.
3.What payment methods are accepted for LTC3548AIDD#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3548AIDD#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3548AIDD#PBF?
LTC3548AIDD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3548AIDD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3548AIDD#PBF?
For technical support, including LTC3548AIDD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3548AIDD#PBF requirements.
6.How does Aetrix verify that LTC3548AIDD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3548AIDD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3548AIDD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3548AIDD#PBF?
All LTC3548AIDD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3548AIDD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3548AIDD#PBF part is unused and in its original packaging.
Return procedure for LTC3548AIDD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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