Analog Devices Inc. LTC3548EDD#PBF
- Part No.:
- LTC3548EDD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC3548EDD#PBF.pdf
- Description:
- IC REG BUCK BOOST ADJ DL 10DFN
- Quantity:
- Payment:

- Shipping:

Inventory:131
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Product details
Overview
LTC3548EDD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel synchronous step-down DC/DC regulator optimized for portable low-power systems. It delivers 400mA and 800mA per channel, operates from 2.5V to 5.5V input, maintains constant 2.25MHz switching frequency, and supports adjustable output voltages from 0.6V to 5V - enabling compact power delivery in PDAs, digital cameras, and cellular phones.
For engineers reviewing the LTC3548EDD#PBF datasheet, LTC3548EDD#PBF pinout, LTC3548EDD#PBF application, or LTC3548EDD#PBF equivalent, key selection criteria include its dual-output burst-mode efficiency (95% peak), 40μA quiescent current, integrated 0.35Ω P-channel MOSFETs, 10-lead 3mm × 3mm DFN package, and Power-On Reset functionality.
Technical Context
The LTC3548EDD#PBF employs a constant-frequency current-mode architecture with shared 2.25MHz oscillator across both channels, enabling precise in-phase switching and stable transient response. Its dual independent control loops use 0.6V internal reference and external resistive feedback dividers to regulate each output independently.
Mode selection via MODE/SYNC pin enables either Burst Mode® (for ultra-low IQ of 40μA at light load) or pulse-skipping mode (for low-noise operation), while 100% duty-cycle dropout operation sustains regulation down to VIN ≈ VOUT. The POR pin provides open-drain reset signaling with –8.5% undervoltage detection and 117ms delay after regulation recovery.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 5.5V - supports single-cell Li-ion, Li-polymer, and 3.3V/5V rail inputs without external LDO pre-regulation. |
| Switching Frequency | 2.25MHz (typ) - enables use of sub-3mm-height inductors and ≤10μF ceramic capacitors for ultra-thin portable designs. |
| Output Current Capability | Channel 1: 800mA; Channel 2: 400mA - supports asymmetric loads like core + I/O rails in handheld devices. |
| Feedback Reference Voltage | 0.6V ±12mV (–40°C to 85°C) - sets output voltage via external resistor divider; enables 0.6V–5V adjustment with <±2% load/line regulation. |
| Quiescent Current | 40μA (typ, both channels active) - extends battery runtime in always-on subsystems such as real-time clocks or sensor interfaces. |
| Shutdown Current | <1μA - ensures negligible battery drain during system sleep or storage modes. |
| Power-On Reset Threshold | –8.5% of regulated output - asserts POR low when either output drops below regulation; 117ms timeout ensures clean system boot sequencing. |
Pinout & Package
Package: 10-lead (3mm × 3mm) plastic DFN with exposed pad (Pin 11 = PGND). Thermally enhanced for 45°C/W junction-to-ambient (θJA) on 4-layer PCBs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VFB1 (Pin 1) | Channel 1 feedback input | Connects to resistor divider; regulates VOUT1 to 0.6V reference; 30nA input bias minimizes divider current loss. |
| RUN1 (Pin 2) | Channel 1 enable control | High = enable; low = shutdown; must be actively driven - floating causes undefined behavior. |
| VIN (Pin 3) | Main power input | Supplies both regulators; requires local 10μF ceramic decoupling to minimize high-frequency noise coupling. |
| SW1 (Pin 4) | Channel 1 switch node | Connects to inductor; swings between VIN and GND; layout critical to minimize EMI and switching losses. |
| GND (Pin 5) | Analog ground reference | Separate from PGND; connects to quiet analog ground plane; not internally tied to exposed pad. |
| MODE/SYNC (Pin 6) | Mode selection & sync input | Ground = pulse-skipping; VIN = Burst Mode®; external clock input synchronizes both channels to external source. |
| SW2 (Pin 7) | Channel 2 switch node | Independent switch node for second buck stage; same voltage swing and layout sensitivity as SW1. |
| POR (Pin 8) | Open-drain power-on reset | Pulled low if either output is out-of-regulation; 100Ω–200Ω on-resistance allows direct MCU reset pin connection. |
| RUN2 (Pin 9) | Channel 2 enable control | Functionally identical to RUN1; enables independent power sequencing of dual-rail systems. |
| VFB2 (Pin 10) | Channel 2 feedback input | Identical to VFB1; supports independent output voltage setting and regulation for second channel. |
Key Features
| Feature | Design Value |
|---|---|
| Dual synchronous buck topology | Eliminates external Schottky diodes; integrates 0.35Ω P-channel high-side and 0.30Ω N-channel low-side MOSFETs per channel. |
| Burst Mode® operation | Reduces quiescent current to 40μA while maintaining regulation - critical for battery-powered standby time. |
| 100% duty-cycle dropout | Enables VOUT operation down to VIN – (IOUT × RDS(ON)) - preserves regulation during brownout or low-battery conditions. |
| Externally synchronizable oscillator | Accepts 2.25MHz external clock on MODE/SYNC pin to eliminate beat frequencies in multi-regulator systems. |
| Integrated Power-On Reset | Monitors both outputs; asserts POR within 117ms of full regulation - eliminates need for discrete reset IC in space-constrained designs. |
Applications
| PDAs / Palmtop PCs | Digital Cameras |
|---|---|
Use Scenario: Dual-rail power for ARM-based application processor (1.2V core) and image signal processor (2.8V I/O). IC Role / Device Role / Timing Role: Primary dual-output DC/DC regulator delivering tightly regulated, sequenced voltages with minimal board area. Use Value: 2.25MHz operation allows 2.2μH/4.7μH inductors and 10μF ceramic caps - reducing solution height to ≤1mm and total footprint to <40mm². | Use Scenario: Powering CMOS image sensor (1.8V analog), DSP (1.2V core), and SD card interface (3.3V) from single Li-ion cell. IC Role / Device Role / Timing Role: Dual synchronous buck converter providing independent, low-noise rails with programmable startup sequencing. Use Value: Burst Mode® extends battery life by >30% during viewfinder standby; POR ensures clean boot before sensor initialization. |
| Cellular Phones | Wireless Modems |
Use Scenario: Supplying RF transceiver (2.8V), baseband processor (1.3V), and memory (1.8V) in slim-profile handset. IC Role / Device Role / Timing Role: High-efficiency dual buck regulator supporting dynamic voltage scaling and rapid load transients. Use Value: 0.35Ω RDS(ON) and current-mode control deliver <100mV output droop during 200mA load steps - meeting GSM/UMTS RF stability requirements. | Use Scenario: Powering LTE modem SoC (1.1V core, 1.8V I/O) and Wi-Fi coexistence circuitry (3.3V) in compact M.2 module. IC Role / Device Role / Timing Role: Compact dual-output regulator enabling single-supply design with independent enable control per rail. Use Value: 10-lead DFN package (3mm × 3mm) fits within tight M.2 edge connector constraints; MODE/SYNC pin allows synchronization to host system clock. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62400DRCT | Single 2-MHz buck with integrated LDO; lower max output current (600mA); no POR or SYNC capability. | Not dual-output; lacks independent enable and reset functions - unsuitable for true dual-rail sequencing. | Select only if system requires one buck + one LDO and can tolerate higher IQ (100μA) and no reset signaling. |
| MAX8646ETE+ | Dual 3-MHz buck; higher IQ (120μA); no Burst Mode®; requires external compensation components. | Higher switching frequency increases EMI risk; no integrated POR or 100% dropout - limits brownout resilience. | Consider only when 3MHz operation is mandatory and external compensation is acceptable for loop tuning. |
Compared with TPS62400DRCT and MAX8646ETE+, the LTC3548EDD#PBF uniquely combines dual independent 2.25MHz buck regulation, 40μA Burst Mode® IQ, integrated POR, and 100% dropout - making it optimal for space-constrained, battery-sensitive dual-rail portable systems where reliability and sequencing integrity are critical.
Availability
LTC3548EDD#PBF is available at Aetrix Electronics and suitable for PDAs, digital cameras, and cellular phones requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for LTC3548EDD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full technical and manufacturing continuity for all Linear power products.
The LTC3548EDD#PBF belongs to Linear's high-frequency synchronous buck regulator product line, designed specifically for ultra-compact, battery-powered portable electronics demanding high efficiency at light loads and robust transient response.
FAQ
What is the maximum recommended PCB temperature rise for reliable operation of the LTC3548EDD#PBF?
The LTC3548EDD#PBF has a maximum junction temperature of 125°C and thermal resistance θJA = 45°C/W on a 4-layer board. To ensure reliable operation, keep ambient temperature plus power-dissipation-induced rise below 125°C. For typical 800mA/400mA loads at 3.6V input, power loss is ~250mW; thus, ambient should remain ≤85°C with ≤40°C PCB temperature rise. Always solder the exposed pad (Pin 11) to a solid ground plane for optimal thermal conduction.
Can the LTC3548EDD#PBF operate with ceramic input and output capacitors only?
Yes, the LTC3548EDD#PBF supports all-ceramic capacitor designs, but requires careful layout and selection. Use X5R or X7R dielectrics (not Y5V), place 0.1μF–1μF high-frequency ceramics close to VIN and SW pins, and avoid excessive capacitance that may destabilize the current-mode loop. The datasheet recommends ≥10μF total CIN and ≥10μF COUT per channel, with ESR <150mΩ to limit ripple to <100mV. Stability must be verified across temperature and load.
How does the POR function behave when only one channel is enabled?
When only one channel is enabled (e.g., RUN2 = GND), the POR pin remains low because the disabled channel is considered out-of-regulation. To assert POR high, both RUN1 and RUN2 must be high *and* both VOUT1 and VOUT2 must be within –8.5% of their target voltages for 117ms. This ensures POR reflects full system readiness - not just partial rail availability - which is essential for safe microprocessor boot sequencing in the LTC3548EDD#PBF.
What is the minimum inductor value recommended for stable operation of the LTC3548EDD#PBF at 800mA output?
For Channel 1 (800mA max), the minimum recommended inductor is 2.2μH when VIN = 3.6V and VOUT = 1.8V, based on ΔIL = 0.3 × IOUT(MAX) = 240mA ripple current and fSW = 2.25MHz. Lower values (e.g., 1.5μH) increase ripple and reduce efficiency in Burst Mode®, while higher values (e.g., 4.7μH) improve ripple but slow transient response. Sumida CDRH3D16-2.2 or Murata LQH32CN1R0M2CB are validated DFN-compatible choices per the LTC3548EDD#PBF datasheet.
Does the LTC3548EDD#PBF support independent voltage setting for each channel?
Yes, the LTC3548EDD#PBF supports fully independent voltage setting via separate feedback networks: VFB1 controls Channel 1 output using R1/R2 divider, and VFB2 controls Channel 2 output using R3/R4 divider. Each uses the same 0.6V internal reference, enabling outputs from 0.6V to 5V. The datasheet confirms no crosstalk between channels - regulation accuracy remains within ±2% for each rail under varying load conditions on the other channel.
LTC3548EDD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down, Step-Up/Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck, Buck-Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5V
- Current - Output:
- 400mA, 800mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
LTC3548EDD#PBF FAQ
1.How can I place an order for LTC3548EDD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3548EDD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3548EDD#PBF reliable?
The price and inventory of LTC3548EDD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3548EDD#PBF is usually 5 days.
3.What payment methods are accepted for LTC3548EDD#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3548EDD#PBF transactions.
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4.How is shipping managed for LTC3548EDD#PBF?
LTC3548EDD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3548EDD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3548EDD#PBF?
For technical support, including LTC3548EDD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3548EDD#PBF requirements.
6.How does Aetrix verify that LTC3548EDD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3548EDD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3548EDD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3548EDD#PBF?
All LTC3548EDD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3548EDD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3548EDD#PBF part is unused and in its original packaging.
Return procedure for LTC3548EDD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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