Analog Devices Inc. LTC3548IDD#TRPBF
- Part No.:
- LTC3548IDD#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC3548IDD#TRPBF.pdf
- Description:
- IC REG BUCK BOOST ADJ DL 10DFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,010
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3548IDD#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel synchronous step-down DC/DC regulator designed for low-power portable systems. It delivers 400mA and 800mA per channel, operates from 2.5V to 5.5V input, maintains constant 2.25MHz switching frequency, and supports adjustable output voltages from 0.6V to 5V - enabling compact power solutions in PDAs, digital cameras, and cellular phones.
For engineers reviewing the LTC3548IDD#TRPBF datasheet, LTC3548IDD#TRPBF pinout, LTC3548IDD#TRPBF application, or LTC3548IDD#TRPBF equivalent, key selection criteria include verified 0.35Ω top-switch RDS(ON), confirmed 40μA quiescent current in active mode, documented Burst Mode® vs pulse-skipping mode trade-offs, and validated 10-lead 3mm × 3mm DFN thermal performance with exposed PGND pad.
Technical Context
The LTC3548IDD#TRPBF implements a constant-frequency current-mode control architecture with shared 2.25MHz oscillator across both channels, enabling precise timing alignment and simplified EMI filtering. Its dual independent feedback loops use 0.6V reference voltage with ±12mV tolerance over –40°C to 85°C, and each channel features dedicated RUN enable inputs and VFB pins for independent regulation.
Operation includes three distinct low-power states: continuous conduction mode (CCM), Burst Mode® (for <1μA shutdown current and peak efficiency at light loads), and pulse-skipping mode (for minimized output ripple). The device integrates P-channel high-side and N-channel low-side MOSFETs with matched RDS(ON) (0.35Ω / 0.30Ω), eliminating external Schottky diodes while supporting 100% duty-cycle dropout operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 5.5V - supports single-cell Li-ion, Li-polymer, and 3.3V/5V rail inputs without pre-regulation. |
| Switching Frequency | 2.25MHz (typ) - enables use of sub-3mm-height inductors (e.g., 2.2μH) and ≤10μF ceramic output capacitors. |
| Output Current Capability | Channel 1: 800mA; Channel 2: 400mA - defined by internal 1.2A/0.7A peak switch current limits with thermal derating. |
| Feedback Reference Voltage | 0.600V ±12mV (–40°C to 85°C) - sets output via external resistor divider; enables precise 0.6V–5V adjustment with <0.5% line/load regulation. |
| Quiescent Current | 40μA (typ) - total for both channels in active mode; extends battery runtime in always-on subsystems. |
| Shutdown Current | <1μA - achieved by pulling RUN1/RUN2 low; critical for zero-power standby in portable devices. |
| Power-On Reset Threshold | –8.5% of regulated output - asserts open-drain POR signal when either channel falls out of regulation; 117ms delay after recovery. |
Pinout & Package
Package: 10-lead (3mm × 3mm) plastic DFN with exposed power ground pad (Pin 11), rated for –40°C to 85°C operating temperature. Requires soldering exposed pad to PCB ground plane for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VFB1 (Pin 1) | Channel 1 feedback input | Connects to resistive divider output; regulates VOUT1 to 0.6V × (1 + R2/R1); input bias current ≤30nA. |
| RUN1 (Pin 2) | Channel 1 enable control | High = enable (VIN level); low = shutdown; must be actively driven - floating causes undefined behavior. |
| VIN (Pin 3) | Main power input | Supplies both channels; requires local 10μF ceramic decoupling; absolute max = 6V. |
| SW1 (Pin 4) | Channel 1 switch node | Connects to inductor; swings between VIN and GND; layout critical for EMI and efficiency. |
| GND (Pin 5) | Analog ground reference | Separate from PGND; connects to PCB ground plane; not internally bonded - must be externally tied. |
| MODE/SYNC (Pin 6) | Mode selection & sync input | VIN = Burst Mode®; GND = pulse-skipping; external clock = synchronization with forced pulse-skipping. |
| SW2 (Pin 7) | Channel 2 switch node | Independent switch node for second converter; identical electrical behavior to SW1. |
| POR (Pin 8) | Power-on reset output | Open-drain logic output; pulled low if either VOUT drops >8.5% below target; 117ms timeout after recovery. |
| RUN2 (Pin 9) | Channel 2 enable control | Functionally identical to RUN1; enables/disables second regulator independently. |
| VFB2 (Pin 10) | Channel 2 feedback input | Identical to VFB1; supports independent output voltage setting for VOUT2. |
| Exposed Pad (Pin 11) | Power ground (PGND) | Mandatory connection to PCB ground plane; primary thermal path; reduces θJA to 45°C/W. |
Key Features
| Feature | Design Value |
|---|---|
| No external Schottky diodes required | Integrated synchronous rectification with 0.35Ω/0.30Ω P/N-channel MOSFETs eliminates conduction losses and board space. |
| Burst Mode® operation | Delivers up to 95% efficiency at 1mA load by gating full switching cycles - reduces IQ to 40μA without compromising regulation. |
| Externally synchronizable oscillator | Accepts 2.25MHz external clock on MODE/SYNC pin to eliminate beat frequencies in multi-rail systems. |
| 100% duty-cycle dropout | P-channel MOSFET remains fully enhanced when VIN ≈ VOUT, maintaining regulation down to (VOUT + VDS(on)) with minimal dropout voltage. |
| Power-On Reset with timeout | Dedicated POR pin asserts low during startup/fault and releases after 262,144 clock cycles (~117ms) only when both outputs are in regulation. |
Applications
| Mobile Baseband Power | Digital Camera Core Logic |
|---|---|
Use Scenario: Dual-rail power for 3G/4G baseband processor requiring 1.8V core and 2.5V I/O rails from single Li-ion cell. IC Role / Device Role / Timing Role: Primary dual-output buck regulator providing tightly regulated, low-noise supplies with independent enable control. Use Value: 2.25MHz operation allows use of 2.2μH/4.7μH shielded inductors ≤1mm height; 40μA quiescent current extends talk time. |
Use Scenario: Power management for CMOS image sensor and ISP in ultra-thin digital camera with strict height constraints. IC Role / Device Role / Timing Role: Compact dual-buck solution delivering 1.2V sensor core and 2.8V analog front-end from 3.6V battery. Use Value: Burst Mode® maintains >85% efficiency at 10mA standby current; exposed DFN pad ensures thermal compliance in sealed enclosure. |
| Wireless Modem RF Front-End | Portable Media Player Audio Codec |
Use Scenario: Isolated power for LTE PA bias and transceiver LNA in PC Card-format wireless modem. IC Role / Device Role / Timing Role: Dual-channel regulator with independent RUN control enables dynamic power gating of RF sections. Use Value: Pulse-skipping mode selected via MODE/SYNC = GND minimizes switching noise coupling into sensitive RF paths. |
Use Scenario: Low-noise dual supply for stereo audio DAC and headphone amplifier in battery-powered media player. IC Role / Device Role / Timing Role: High PSRR buck regulator pair generating 1.8V digital and 3.3V analog rails from shared 4.2V battery. Use Value: 0.6V reference accuracy (±2%) and <0.5% load regulation ensure consistent DAC reference stability across battery discharge. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS62400DRVR | 2.25MHz fixed frequency; 600mA/600mA outputs; 0.6V reference; no POR output; 0.45Ω RDS(ON). | Lacks power-on reset functionality and independent RUN control per channel; lower max output current per rail. | Choose when POR is unnecessary and symmetrical 600mA rails suffice; verify thermal performance with 0.45Ω switches. |
| MAX17504ATJ+T | 2.1MHz frequency; 1A/1A outputs; 0.6V reference; integrated soft-start; no Burst Mode®; 0.25Ω RDS(ON). | Higher current capability but lacks low-IQ Burst Mode®; uses pulse-frequency modulation instead of burst gating. | Prefer for higher-load applications where 40μA quiescent current is not required; confirm EMI profile without burst discontinuity. |
Compared with TPS62400DRVR and MAX17504ATJ+T, the LTC3548IDD#TRPBF uniquely combines dual asymmetric current capability (400mA/800mA), integrated POR with timeout, and selectable Burst Mode®/pulse-skipping - making it optimal for space-constrained portable devices needing precise sequencing and ultra-low standby power.
Availability
LTC3548IDD#TRPBF is available at Aetrix Electronics and suitable for mobile computing, imaging systems, and wireless communications requiring stable component supply, long-term lifecycle support, and guaranteed DFN package consistency.
Supply support for LTC3548IDD#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its precision power portfolio. Linear pioneered high-efficiency, high-frequency DC/DC conversion for portable electronics.
The LTC3548IDD#TRPBF belongs to Linear's µPower synchronous buck regulator family, engineered specifically for battery-powered handheld devices demanding minimal quiescent current, small solution size, and robust light-load efficiency.
FAQ
What is the maximum allowable input voltage for the LTC3548IDD#TRPBF?
The LTC3548IDD#TRPBF has an absolute maximum input voltage rating of 6V, but its specified operating range is 2.5V to 5.5V. Exceeding 5.5V may cause permanent damage or violate safety margins. For reliable operation with Li-ion batteries, design with VIN ≤5.5V including worst-case charging voltage tolerance.
Does the LTC3548IDD#TRPBF require external compensation components?
No, the LTC3548IDD#TRPBF uses internal compensation optimized for standard ceramic output capacitors. External feed-forward capacitor CF is optional and only recommended if enhanced transient response is needed - the device functions correctly with just the feedback resistors and standard COUT.
How does the POR function behave when only one channel is enabled?
When only one channel is enabled, the POR pin of the LTC3548IDD#TRPBF remains low because the unpowered channel is considered out of regulation. To assert POR only upon valid dual-rail startup, both RUN1 and RUN2 must be high before the 117ms timeout begins counting.
Can the LTC3548IDD#TRPBF operate with ceramic input and output capacitors exclusively?
Yes, the LTC3548IDD#TRPBF is designed for ceramic capacitors, but layout and capacitor selection are critical. Use X5R/X7R dielectrics, avoid undersized ceramics (<1μF) on VIN, and add 0.1μF high-frequency bypass caps near SW pins to prevent ringing-induced instability or overstress.
What thermal considerations apply to the exposed pad on the LTC3548IDD#TRPBF DFN package?
The exposed pad (Pin 11) of the LTC3548IDD#TRPBF is PGND and must be soldered to a minimum 100mm² copper area on inner PCB layers. With proper 4-layer board implementation, θJA is 45°C/W - insufficient copper or missing thermal vias will cause junction temperature to exceed 125°C under 800mA load at 5.5V input.
LTC3548IDD#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down, Step-Up/Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck, Buck-Boost
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5V
- Current - Output:
- 400mA, 800mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
LTC3548IDD#TRPBF FAQ
1.How can I place an order for LTC3548IDD#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3548IDD#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3548IDD#TRPBF reliable?
The price and inventory of LTC3548IDD#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3548IDD#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC3548IDD#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3548IDD#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3548IDD#TRPBF?
LTC3548IDD#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3548IDD#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3548IDD#TRPBF?
For technical support, including LTC3548IDD#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3548IDD#TRPBF requirements.
6.How does Aetrix verify that LTC3548IDD#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC3548IDD#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3548IDD#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC3548IDD#TRPBF?
All LTC3548IDD#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3548IDD#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3548IDD#TRPBF part is unused and in its original packaging.
Return procedure for LTC3548IDD#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3548IDD#TRPBF Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
