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Analog Devices Inc. LTC3569EUDC#PBF
- Part No.:
- LTC3569EUDC#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 20-WFQFN Exposed Pad
- Datasheet:
-
LTC3569EUDC#PBF.pdf
- Description:
- IC REG BUCK ADJ TRPL 20QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,175
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Product details
Overview
LTC3569EUDC#PBF from Analog Devices (formerly Linear Technology) is a triple monolithic synchronous step-down DC/DC regulator IC with one 1.2A and two 600mA buck outputs, operating from 2.5V to 5.5V input, programmable 1MHz–3MHz switching frequency, and independent 800mV–425mV feedback references for dynamic voltage scaling in portable multi-rail systems.
For engineers reviewing the LTC3569EUDC#PBF datasheet, LTC3569EUDC#PBF pinout, LTC3569EUDC#PBF application, or LTC3569EUDC#PBF equivalent, key selection criteria include per-buck enable-programmable reference, slave-mode parallel configuration capability, Burst Mode® vs pulse-skipping trade-offs, thermal performance in 3mm × 4mm QFN, and PGOOD logic-AND behavior across enabled outputs.
Technical Context
The LTC3569EUDC#PBF integrates three current-mode buck regulators with internal P/N-channel MOSFETs, each featuring independent soft-start, 100% duty-cycle dropout operation, and programmable reference via EN-pin toggling. Its MODE pin selects between Burst Mode® (optimized efficiency <10mA) and pulse-skipping (lower ripple), while RT pin sets oscillator frequency or enables synchronization to external clock (1.2–3MHz).
Each buck supports slave configuration: FB2 tied to SVIN makes Buck 2 follow Buck 1; FB3 tied to SVIN makes Buck 3 follow Buck 2. Slave mode requires corresponding ENx high and shares inductor/inductor current path, enabling 1.8A (Buck1+Buck2) or 1.2A+600mA configurations without external power stage duplication.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 5.5V - supports single-cell Li-ion, USB VBUS, and regulated intermediate rails without external LDO pre-regulation. |
| Output Current Capability | 1.2A (Buck1), 600mA (Buck2), 600mA (Buck3) - enables independent powering of core, I/O, and memory rails in SoC-based portable devices. |
| Feedback Reference Range | 800mV to 425mV in 25mV steps - allows precise dynamic voltage scaling for processors and FPGAs via simple EN-pin toggling, no I²C required. |
| Switching Frequency | 1MHz to 3MHz (programmable) or fixed 2.25MHz - permits use of sub-3mm inductors and low-ESR ceramic capacitors, reducing board area and cost. |
| Quiescent Current | <100µA (all bucks in Burst Mode) - extends battery life in always-on subsystems such as RTC, sensors, or BLE radio sleep states. |
| Protection Features | Overtemperature shutdown (150°C), short-circuit protection, undervoltage lockout (2.5V), and PGOOD with 8%/12% hysteresis - ensures robust operation under fault and brownout conditions. |
| Package Thermal Resistance | θJA = 43°C/W (UDC 3mm × 4mm QFN) - enables 1.2A continuous output at TA = 85°C with minimal PCB copper area. |
Pinout & Package
Package: 20-lead (3mm × 4mm) plastic QFN (LFYW), exposed pad soldered to PCB ground for thermal and electrical integrity. Pin 1 marked by dot; pin 21 = exposed pad = GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| EN1, EN2, EN3 | Enable & reference programming inputs | Toggle falling edge counts down internal DAC to set FBx reference from 800mV to 425mV; also enable/disable respective buck regulator. |
| FB1, FB2, FB3 | Feedback inputs | Monitor output voltage divider ratio; FB2/FB3 pulled to SVIN configures Buck2/Buck3 as slaves to Buck1/Buck2 respectively. |
| SW1, SW2, SW3 | Power switch nodes | Connect to respective inductors; swing between PVINx and PGNDx; require low-inductance layout to minimize EMI and switching losses. |
| PVIN1, PVIN2, PVIN3 | Main power inputs per buck | Decoupled individually to respective PGND pins with ≥4.7µF low-ESR ceramics; shared PVINx reduces input capacitance when bucks operate in phase. |
| PGND1, PGND2, PGND3 | Power ground returns | Separate ground paths prevent cross-regulator noise coupling; must connect to local output capacitor negatives and CINx cathodes. |
| MODE | Mode select & sync input | Tied to SVIN → Burst Mode; tied to SGND → pulse-skipping; driven with >100ns pulses → synchronizes to external clock (1.2–3MHz). |
| RT | Oscillator timing resistor | Resistor to GND sets free-running frequency (1–3MHz); tied to SVIN → fixed 2.25MHz operation. |
| PGOOD | Open-drain power-good flag | Active-low; asserts only when *all* enabled outputs reach ±8% of target; logical AND of internal PGOOD signals. |
| SVIN, SGND | Main supply & signal ground | SVIN powers internal circuitry and bias; SGND is reference for FB, EN, MODE, RT; must be low-impedance connection to exposed pad. |
Key Features
| Feature | Design Value |
|---|---|
| Triple independent buck regulation | Enables compact, low-noise multi-rail power architecture for SoCs with separate core, I/O, and memory domains - eliminates need for three discrete converters. |
| Single-pin reference programming | Eliminates external DAC or I²C interface; EN-pin toggling provides 15-step (25mV) adjustment of each FB reference - simplifies firmware control and reduces BOM count. |
| Configurable slave-mode parallel operation | Allows Buck2 to mirror Buck1 or Buck3 to mirror Buck2, enabling 1.8A (Buck1+Buck2) or 1.2A+600mA outputs using shared inductor and feedback - saves board space and component cost. |
| Burst Mode® with <100µA IQ | Maintains high efficiency down to µA load levels in always-on circuits (e.g., real-time clocks, sensor hubs) without sacrificing regulation accuracy or requiring external disable sequencing. |
| 100% duty-cycle dropout operation | Supports ultra-low VIN–VOUT differentials (e.g., 3.3V input → 3.0V output) without dropout-induced reset or brownout - critical for battery-powered systems near end-of-discharge. |
Applications
| Mobile Application Processor Power | Multi-Rail FPGA Core/I/O Supply |
|---|---|
Use Scenario: Powering ARM Cortex-A series SoCs with dynamically scaled core (VDD_CPU), GPU (VDD_GPU), and memory interface (VDD_IO) rails from single-cell Li-ion battery. IC Role / Device Role / Timing Role: LTC3569EUDC#PBF delivers three independently regulated, dynamically scalable outputs with synchronized soft-start and coordinated PGOOD assertion. Use Value: Reduces total solution size by 40% vs discrete buck ICs; enables DVFS-driven battery life extension via real-time EN-pin reprogramming without system reset. | Use Scenario: Supplying Xilinx Artix-7 FPGA requiring 1.0V core, 1.8V auxiliary, and 3.3V I/O rails with tight transient response and rail sequencing. IC Role / Device Role / Timing Role: LTC3569EUDC#PBF provides independent enable/control per rail, PGOOD AND logic for safe configuration loading, and slave-mode option for high-current core rail. Use Value: Eliminates external sequencing IC and reduces component count by consolidating three regulators into one thermally optimized QFN package. |
| Wearable Sensor Hub Power | Industrial IoT Edge Node |
Use Scenario: Powering ultra-low-power wearable system with BLE SoC (1.8V), MEMS sensor array (3.3V), and optical heart-rate monitor (2.8V) from coin cell or small Li-Po. IC Role / Device Role / Timing Role: LTC3569EUDC#PBF operates in Burst Mode® across all rails to maintain µA-level quiescent current while delivering precise, low-noise outputs during active sensing bursts. Use Value: Extends coin-cell lifetime beyond 12 months by minimizing no-load IQ and enabling rail-specific enable/disable via simple GPIO control. | Use Scenario: Powering industrial edge node with Cortex-M7 MCU (1.2V), RS-485 transceiver (3.3V), and isolated ADC (5.0V derived from 12V input via external pre-regulator). IC Role / Device Role / Timing Role: LTC3569EUDC#PBF supplies MCU core and interface rails from intermediate 3.3V/5V bus; leverages PGOOD to gate firmware initialization until all rails are stable. Use Value: Ensures deterministic boot sequence and prevents latch-up in mixed-signal systems by providing hardware-enforced power-good coordination across critical rails. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS650703RSLR | Fixed 1.2A + 0.6A + 0.6A outputs; no EN-pin reference programming; uses I²C for voltage setting; 2.7–5.5V input; 2.25MHz fixed frequency. | Requires microcontroller I²C interface and firmware overhead; lacks toggle-based analog programming; better suited for systems with existing I²C infrastructure and need for fine-grained (10mV) voltage control. | Select TPS650703RSLR when digital voltage control, integrated LDOs, or factory calibration via EEPROM are required - not for pin-compatible replacement. |
| ISL9305IRTNZ-T | 1.2A + 0.6A dual-buck (no third output); supports 0.3–3.6V output range; 2.5–5.5V input; 1.5–4MHz programmable frequency; no slave-mode capability. | Lacks third output and slave configuration; limited to dual-rail systems; higher minimum output voltage (0.3V) but wider max (3.6V); smaller 3mm × 3mm package. | Select ISL9305IRTNZ-T when only two rails are needed and board space is more constrained than feature count - not a functional substitute for triple-output requirement. |
Compared with TPS650703RSLR and ISL9305IRTNZ-T, the LTC3569EUDC#PBF uniquely combines three independent buck outputs, analog EN-pin reference programming, and configurable slave-mode parallel operation in a single 3mm × 4mm QFN - making it the only option for compact, firmware-light, dynamically scalable triple-rail designs.
Availability
LTC3569EUDC#PBF is available at Aetrix Electronics and suitable for portable electronics, wearable sensor hubs, and industrial IoT edge nodes requiring stable component supply, long-term lifecycle support, and guaranteed -40°C to +125°C operation.
Supply support for LTC3569EUDC#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (ADI) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, formed through the acquisition of Linear Technology in 2017.
The LTC3569EUDC#PBF belongs to ADI's Power by Linear™ family of highly integrated DC/DC regulators, designed specifically for space-constrained, battery-powered applications demanding high efficiency, low IQ, and flexible multi-rail power architecture.
FAQ
What is the maximum output current capability of each buck regulator in the LTC3569EUDC#PBF?
The LTC3569EUDC#PBF provides up to 1.2A from Buck 1 (SW1/PVIN1 path), and up to 600mA each from Buck 2 (SW2/PVIN2) and Buck 3 (SW3/PVIN3). Peak inductor current limits are 2.0A (Buck1) and 1.0A (Buck2/Buck3), verified across temperature. When configured in slave mode, Buck2 can deliver up to 1.8A when paralleled with Buck1 using shared inductor and feedback network - confirmed in the LTC3569 datasheet Figure 10 and Section "Slave Power Stage".
How does the EN-pin toggling mechanism program the feedback reference voltage in the LTC3569EUDC#PBF?
The LTC3569EUDC#PBF uses falling-edge toggles on EN1/EN2/EN3 to decrement an internal 4-bit DAC counter, lowering the respective FBx reference from 800mV down to 425mV in 25mV steps (15 steps total). Each toggle requires ≥60ns pulse width and ≤55µs high time; after 125µs high, the counter latches and loads the DAC. Holding ENx low for ≥170µs resets to full-scale 800mV - detailed in datasheet Sections "Programming the Reference" and Figure 3.
Can the LTC3569EUDC#PBF operate with input voltage below 2.5V?
No. The LTC3569EUDC#PBF incorporates undervoltage lockout (UVLO) that disables all regulators when SVIN drops below 2.5V (typical), preventing unstable operation or unregulated output. This threshold is absolute - no operation is guaranteed below 2.5V, and the device remains in shutdown until SVIN rises above UVLO hysteresis (~2.55V). This behavior is specified in Absolute Maximum Ratings and Electrical Characteristics tables.
What thermal performance can be expected from the LTC3569EUDC#PBF in its UDC (3mm × 4mm QFN) package?
The LTC3569EUDC#PBF in the LFYW 20-lead 3mm × 4mm QFN package has θJA = 43°C/W (JEDEC High-K board). With the exposed pad soldered to ≥1cm² PCB ground plane, it sustains 1.2A continuous output at ambient temperatures up to 85°C. Junction temperature rise is calculated as ΔT = Pdiss × θJA; typical power dissipation at 1.2A/2.5V out from 3.6V in is ~350mW, yielding ~15°C rise - well within the 125°C max junction rating. Thermal shutdown activates at 150°C.
Does the LTC3569EUDC#PBF support synchronization to an external clock, and what are the requirements?
Yes. The MODE pin of the LTC3569EUDC#PBF accepts an external clock for synchronization across 1.2MHz to 3MHz. The input must be a logic-level square wave with minimum high/low pulse widths of 100ns, referenced to SGND. Synchronization forces pulse-skipping mode regardless of MODE DC level. When synchronized, the internal oscillator is disabled and switching edges align to the external clock - confirmed in Electrical Characteristics table (fSYNC) and Operation section "MODE: Combination Mode Selection…".
LTC3569EUDC#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 20-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 3
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.425V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 600mA, 1.2A
- Frequency - Switching:
- 2.25MHz, 1MHz ~ 3MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-QFN (3x4)
LTC3569EUDC#PBF FAQ
1.How can I place an order for LTC3569EUDC#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3569EUDC#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3569EUDC#PBF reliable?
The price and inventory of LTC3569EUDC#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3569EUDC#PBF is usually 5 days.
3.What payment methods are accepted for LTC3569EUDC#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3569EUDC#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3569EUDC#PBF?
LTC3569EUDC#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3569EUDC#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3569EUDC#PBF?
For technical support, including LTC3569EUDC#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3569EUDC#PBF requirements.
6.How does Aetrix verify that LTC3569EUDC#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3569EUDC#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3569EUDC#PBF meets industry standards.
7.What is the process for return or replacement of LTC3569EUDC#PBF?
All LTC3569EUDC#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3569EUDC#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3569EUDC#PBF part is unused and in its original packaging.
Return procedure for LTC3569EUDC#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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