Analog Devices Inc. LTC3610IWP
- Part No.:
- LTC3610IWP
- Manufacturer:
- Analog Devices Inc.
- Package:
- 64-PowerVFQFN
- Datasheet:
-
LTC3610IWP.pdf
- Description:
- IC REG BUCK ADJ 12A 64QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,850
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3610IWP from Analog Devices (formerly Linear Technology) is a monolithic synchronous step-down DC/DC converter delivering up to 12A output current from a 4V to 24V input, featuring valley current mode control, programmable on-time, adjustable current limit, and ±1% 0.6V reference voltage - deployed in point-of-load regulation for FPGA, ASIC, and DSP power rails.
For engineers reviewing the LTC3610IWP datasheet, LTC3610IWP pinout, LTC3610IWP application, or LTC3610IWP equivalent, key selection criteria include minimum on-time (≤100ns), forced continuous/discontinuous mode control via FCB pin, VRNG-programmable valley current limit (7–19A), 9mm × 9mm 64-pin QFN thermal performance, and EXTVCC-supported high-efficiency gate drive sourcing.
Technical Context
The LTC3610IWP implements a constant on-time, valley current mode architecture where switching frequency is implicitly set by ION current and VON voltage, enabling stable operation across wide VIN/VOUT ratios without external compensation. Its internal N-channel MOSFETs (12mΩ top / 6.5mΩ bottom) support high-efficiency synchronous rectification and eliminate external diode requirements.
Fault protection includes foldback current limiting triggered by VFB drop, output overvoltage detection (±10% window), undervoltage lockout (3.4V–4.0V hysteresis), and optional short-circuit shutdown timer via RUN/SS pin configuration. Power good (PGOOD) provides open-drain status signaling with ±10% hysteresis relative to VFB.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 12A max continuous output current at full thermal derating in 9mm × 9mm QFN package. |
| Input Voltage Range | 4V to 24V operating range; absolute max 28V - supports industrial 12V/24V bus systems. |
| Feedback Reference | 0.600V ±1% over –40°C to 125°C - enables precise 2.5V, 3.3V, or 5V output setting with standard resistor dividers. |
| Minimum On-Time | 60ns to 100ns - enables high step-down ratios (e.g., 24V→2.5V at ~500kHz) without dropout. |
| Valley Current Limit | Programmable 7A–19A via VRNG pin voltage (0.5V–0.7V) - sets peak inductor current and short-circuit foldback threshold. |
| Shutdown IQ | 15µA typical - ensures ultra-low system standby power in battery-backed or always-on applications. |
| Thermal Rating | Junction temperature rated to 125°C; θJA = 28°C/W on JESD51-7 board - requires thermal pad soldering and PCB copper pour for full 12A capability. |
Pinout & Package
Package: 64-lead (9mm × 9mm) plastic QFN with exposed thermal pad (WP suffix). Requires soldering of PGND pins (1,2,3,56–65) and thermal pad to maximize power dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PGND (1,2,3,56–65) | Power Ground | Low-impedance return path for high-current switch node and input capacitor - must connect directly to CIN(–) and CVCC(–). |
| SW (4,5,6,7,8,9,10,11,26,55,66) | Switch Node | Drain connection of internal high-side MOSFET and source of low-side MOSFET - routes high di/dt current to inductor and bootstrap capacitor. |
| PVIN (12–25,67) | Main Input Supply | Distributed VIN input pins reduce IR drop and EMI - decouple each group locally with ≥10µF ceramic + bulk capacitance. |
| SGND (28,31,32,33,34,40,42,45–50,68) | Signal Ground | Reference for feedback, error amplifier, and soft-start - tie to PGND at single point near INTVCC/CVCC decoupling. |
| ITH (38) | Error Amplifier Output / Current Threshold | 0–2.4V control voltage setting valley current limit - also used for loop compensation with RC network to VFB. |
| VRNG (37) | Current Limit Range Input | 0.5V–0.7V analog programming input - scales maximum valley current from 7A to 19A linearly. |
| RUN/SS (30) | Enable & Soft-Start Control | 0.8V shutdown threshold; 1.5V turn-on threshold; external capacitor sets ramp time (~3s/µF) and latchoff delay. |
| PGOOD (36) | Power Good Monitor | Open-drain output pulled low when VFB exits ±10% regulation window - drives enable inputs of downstream rails or microcontroller GPIO. |
Key Features
| Feature | Design Value |
|---|---|
| Valley Current Mode Control | Enables fast transient response and inherent cycle-by-cycle current limiting without slope compensation. |
| Programmable Minimum On-Time | Configurable via ION resistor and VON voltage - maintains stable frequency across VIN and VOUT changes. |
| Forced Continuous / Discontinuous Mode | Selectable via FCB pin (0V = forced continuous; INTVCC = discontinuous) - balances light-load efficiency vs EMI/noise. |
| Integrated Gate Drivers | Internal drivers support 5V INTVCC or external EXTVCC (up to 7V) - eliminates need for external driver ICs or bootstrapping complexity. |
| True Current Limit Foldback | Reduces valley current to ~1/6 of max when VFB drops below regulation - protects MOSFETs during sustained short-circuit events. |
| Stable with Ceramic Output Capacitors | No ESR requirement - enables use of low-profile, high-RMS ceramic arrays for compact, low-ripple POL designs. |
Applications
| Server CPU Core Voltage Regulation | FPGA I/O Bank Power |
|---|---|
Use Scenario: Regulating 0.85V–1.2V core supply for multi-core Xeon or AMD EPYC processors under dynamic load steps up to 10A/µs. IC Role / Device Role / Timing Role: Primary POL regulator with valley current mode control and <100ns minimum on-time enabling 24V→1V conversion at 500kHz. Use Value: Delivers 12A with <±1% output accuracy and <1% load regulation - meets VR14/IMVP specifications without external DAC or telemetry interface. | Use Scenario: Powering 1.8V or 2.5V I/O banks on high-pin-count Artix/Kintex Ultrascale+ FPGAs with simultaneous switching noise constraints. IC Role / Device Role / Timing Role: High-current, low-noise buck converter configured in forced continuous mode (FCB = GND) to suppress subharmonic oscillation and EMI. Use Value: Achieves >92% efficiency at 8A/2.5V with ceramic output caps - eliminates electrolytic bulk capacitors and reduces board area by 35% vs discrete solutions. |
| Industrial PLC Backplane Power | Medical Imaging Sensor Array Supply |
Use Scenario: Generating isolated 3.3V/5V rails from 24V DC backplane in DIN-rail mounted PLCs with extended temperature (-40°C to 125°C) operation. IC Role / Device Role / Timing Role: Main 12A step-down stage feeding downstream LDOs or secondary converters - leverages EXTVCC to derive gate drive from local 5V rail. Use Value: Maintains regulation across 4V–24V input transients (e.g., brownouts, load dumps) with UVLO hysteresis and PGOOD sequencing confirmation. | Use Scenario: Biasing CMOS image sensor arrays requiring ultra-low noise, ripple-free 2.5V supply with fast transient recovery (<10µs) during pixel readout bursts. IC Role / Device Role / Timing Role: Low-noise POL regulator using discontinuous mode (FCB = INTVCC) and feedforward capacitor C1 to enhance PSRR above 1MHz. Use Value: Limits output voltage deviation to <±5mV during 0A→8A load steps - prevents pixel corruption and enables 16-bit ADC linearity in ultrasound/MRI front-ends. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-current synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP8770GQ-Z | 6A max output, 2.5V–18V input, integrated compensation, no VRNG/ION programmability | Lacks valley current mode, fixed 500kHz switching, no programmable current limit or soft-start timing | Lower-cost option for fixed 5V/3.3V rails ≤6A where design flexibility and transient performance are secondary. |
| TPS546D24RQV | 15A output, 4.5V–18V input, PMBus interface, digital loop compensation, 3.3mm × 4.5mm QFN | Requires external EEPROM for configuration, higher BOM cost, no EXTVCC support, smaller thermal footprint | Better for digitally managed systems needing telemetry, margining, or multi-rail coordination - not drop-in compatible due to pinout and control interface differences. |
Compared with MP8770GQ-Z and TPS546D24RQV, the LTC3610IWP offers superior transient response via valley current mode, wider input range (4V–24V), analog programmability (VRNG, ION, VON), and proven 12A capability in industrial temperature grade - making it optimal for analog-intensive, high-reliability POL designs where digital overhead is unnecessary.
Availability
LTC3610IWP is available at Aetrix Electronics and suitable for server CPU core voltage regulation, FPGA I/O bank power, and industrial PLC backplane power requiring stable component supply across extended temperature and long production lifecycles.
Supply support for LTC3610IWP includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors.
The LTC3610 product line delivers monolithic high-current synchronous buck regulators optimized for point-of-load applications demanding precision, speed, and ruggedness in space-constrained industrial and computing environments.
FAQ
What is the maximum junction temperature specification for the LTC3610IWP?
The LTC3610IWP has a maximum junction temperature (TJMAX) of 125°C, guaranteed over the full –40°C to 125°C operating junction temperature range. Thermal design must ensure TJ ≤ 125°C under worst-case load, ambient, and airflow conditions - verified using θJA = 28°C/W on JESD51-7 test board and proper thermal pad soldering. The LTC3610IWP datasheet specifies derating curves for output current versus temperature.
How does the VRNG pin adjust current limit on the LTC3610IWP?
The VRNG pin on the LTC3610IWP accepts a voltage from 0.5V to 0.7V to scale the maximum valley current linearly from 7A to 19A. When tied to ground, VRNG defaults to 0.7V (19A typical). An external resistive divider from INTVCC (5V) sets intermediate values - e.g., 0.6V yields ~13A. Floating VRNG is prohibited; the LTC3610IWP will not operate reliably without a defined VRNG voltage.
Can the LTC3610IWP operate with only ceramic output capacitors?
Yes, the LTC3610IWP is explicitly designed to be stable with ceramic output capacitors and requires no minimum ESR. Its valley current mode architecture and internal compensation eliminate the need for electrolytic or polymer bulk capacitors - enabling compact, low-ripple, high-RMS POL designs using multilayer ceramic arrays (MLCCs) for COUT.
What is the purpose of the FCB pin on the LTC3610IWP?
The FCB (Forced Continuous Bias) pin on the LTC3610IWP selects light-load operation mode: grounding FCB forces continuous conduction mode (reducing audible noise and EMI), while tying FCB to INTVCC enables discontinuous mode (improving light-load efficiency). A resistive divider from a secondary output allows automatic mode switching in multi-output designs - all configurable without changing the LTC3610IWP's core topology.
Does the LTC3610IWP support external clock synchronization?
No, the LTC3610IWP does not support external clock synchronization. Its switching frequency is determined solely by the ION resistor and VON voltage via its one-shot on-time generator - a self-timed architecture that provides inherent jitter immunity and eliminates need for sync pins or PLL circuitry. Frequency variation remains within ±10% across line, load, and temperature per the LTC3610IWP datasheet specifications.
LTC3610IWP Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 64-PowerVFQFN
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 1
- Voltage - Input (Min):
- 4V
- Voltage - Input (Max):
- 24V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 24V
- Current - Output:
- 12A
- Frequency - Switching:
- -
- Synchronous Rectifier:
- No
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 64-QFN (9x9)
LTC3610IWP FAQ
1.How can I place an order for LTC3610IWP through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3610IWP on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3610IWP reliable?
The price and inventory of LTC3610IWP are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3610IWP is usually 5 days.
3.What payment methods are accepted for LTC3610IWP?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3610IWP transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3610IWP?
LTC3610IWP orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3610IWP order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3610IWP?
For technical support, including LTC3610IWP datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3610IWP requirements.
6.How does Aetrix verify that LTC3610IWP is sourced from the original manufacturer or authorized distributors?
All LTC3610IWP products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3610IWP meets industry standards.
7.What is the process for return or replacement of LTC3610IWP?
All LTC3610IWP units undergo pre-shipment inspection (PSI). If there is an issue with LTC3610IWP, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3610IWP part is unused and in its original packaging.
Return procedure for LTC3610IWP:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3610IWP Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

