Analog Devices Inc. LTC3615EFE-1#TRPBF
- Part No.:
- LTC3615EFE-1#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 24-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC3615EFE-1#TRPBF.pdf
- Description:
- IC REG BUCK ADJ 3A DL 24TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,344
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Product details
Overview
LTC3615EFE-1#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel, synchronous step-down DC/DC converter IC with 3A per channel output capability, operating up to 4MHz switching frequency and supporting 140°/180° inter-channel phase shift. It features ±1% output voltage accuracy, 0.6V minimum output, and 100% duty cycle low-dropout operation - ideal for point-of-load regulation in portable computing and DDR memory termination systems.
For engineers reviewing the LTC3615EFE-1#TRPBF datasheet, LTC3615EFE-1#TRPBF pinout, LTC3615EFE-1#TRPBF application, or LTC3615EFE-1#TRPBF equivalent, this page delivers verified specifications, validated pin functions, confirmed thermal and electrical behavior across –40°C to 125°C, and real-world design context for dual-rail power delivery in space-constrained Li-ion powered systems.
Technical Context
The LTC3615EFE-1#TRPBF implements current-mode, constant-frequency control with independent PVIN1/PVIN2 inputs and shared SVIN-supplied control logic. Its dual 3A channels support selectable 140° or 180° phase shift via the PHASE pin, minimizing input ripple in dual-output configurations and enabling single 6A output with interleaved operation.
It integrates synchronous P-channel/N-channel MOSFETs (75mΩ/55mΩ typical RDS(ON)), programmable slew rate limiting via SRLIM, and four operating modes (Burst, Pulse-Skipping, Forced Continuous, DDR) selected by the MODE pin - with internal AVP and tracking capability enabled through ITH/TRACK pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.25V to 5.5V - supports single-cell Li-ion battery operation without external pre-regulation. |
| Output Current per Channel | 3A continuous - enables compact dual-rail POL supplies for processors, FPGAs, or DDR memory subsystems. |
| Switching Frequency | Up to 4MHz - permits use of sub-1µH inductors and reduces solution footprint significantly. |
| Output Voltage Accuracy | ±1% over temperature - ensures stable core voltage regulation critical for high-speed digital loads. |
| Quiescent Current (Burst Mode) | 130µA - extends battery runtime in standby or light-load states without sacrificing regulation. |
| Phase Shift Options | 140° or 180° - reduces input capacitor RMS current and output voltage ripple in dual-channel mode. |
| Shutdown Current | ≤1µA - enables true system-level power gating for ultra-low-power sleep states. |
Pinout & Package
Package: 24-pin thermally enhanced plastic TSSOP (FE package), 4mm × 6.5mm body, exposed PGND pad (Pin 25) requiring PCB soldering for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PHASE (Pin 1) | Phase shift selection | Configures 140° (tied to SGND) or 180° (tied to SVIN) inter-channel timing - critical for ripple cancellation. |
| VFB1/VFB2 (Pins 2,5) | Feedback input | Monitors output voltage via resistive divider; sets regulation point at 0.6V reference with ±1% accuracy. |
| ITH1/ITH2 (Pins 3,6) | Error amplifier compensation | Accepts external RC network or ties to SVIN for internal AVP - determines loop stability and transient response. |
| RUN1/RUN2 (Pins 11,10) | Channel enable | Logic-high (>1V) enables respective channel; both low disables entire IC with ≤1µA shutdown current. |
| RT/SYNC (Pin 12) | Oscillator control | Sets frequency via resistor-to-GND (400kHz–4MHz), syncs to external clock, or defaults to 2.25MHz when tied to SVIN. |
| SRLIM (Pin 14) | Slew rate / DDR mode control | Tied to SVIN enables DDR termination mode; resistor-to-SGND adjusts switch edge rate to reduce EMI. |
| PGOOD1/PGOOD2 (Pins 15,13) | Power good indicator | Open-drain outputs pulled low if VFBx deviates >±7.5% - used for sequencing and fault reporting. |
| PGND (Pin 25) | Power ground | Exposed thermal pad connected to sources of N-MOSFETs - must be soldered to PCB plane for θJA = 33°C/W. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3A synchronous buck architecture | Eliminates external catch diodes, improves efficiency to 94%, and reduces BOM count and board area. |
| 140°/180° selectable phase shift | Reduces input capacitor RMS current by up to 40% in dual-output configuration, lowering thermal stress. |
| Programmable slew rate limiting | Adjusts SW1/SW2 edge rates via SRLIM resistor - directly suppresses conducted EMI without filter redesign. |
| Four operational modes (Burst, PS, FCM, DDR) | Enables optimal trade-off between light-load efficiency (130µA), output ripple (FCM), and sink capability (DDR/FCM). |
| Active Voltage Positioning (AVP) | Internal AVP mode (ITH tied to SVIN) dynamically lowers VOUT under load to reduce IR drop and power loss. |
| Accurate start-up tracking | TRACK/SS pins allow synchronized ramp-up with other rails - prevents latch-up and ensures safe FPGA/CPU boot. |
Applications
| Point-of-Load Regulation | DDR Memory Termination |
|---|---|
Use Scenario: Regulating core voltage for low-power ARM SoCs in handheld devices with tight thermal constraints. IC Role / Device Role / Timing Role: Dual-channel buck controller delivering 1.8V/3A and 2.5V/3A simultaneously with interleaved 180° phase. Use Value: 94% peak efficiency and 130µA quiescent current extend battery life while maintaining ±1% output accuracy under dynamic load. |
Use Scenario: Providing VTT termination supply for DDR3/DDR4 memory interfaces requiring ±1.5A sink/source capability. IC Role / Device Role / Timing Role: Configured in DDR mode (SRLIM = SVIN) with forced continuous operation to support bidirectional current flow. Use Value: Internal AVP and accurate tracking ensure VTT tracks VDDQ within 1%, minimizing signal integrity risk during memory access bursts. |
| Portable Computer Systems | Distributed Power Supplies |
Use Scenario: Generating multiple independent rails (e.g., CPU core, GPU, I/O) from a single 3.3V or 5V intermediate bus. IC Role / Device Role / Timing Role: Dual-channel regulator with independent RUN/TRACK pins enabling precise power sequencing and fault isolation. Use Value: Programmable soft-start and PGOOD outputs simplify compliance with Intel IMVP or AMD SVI2 sequencing requirements. |
Use Scenario: Distributed 3A rails across multi-board industrial controllers where layout constraints limit centralized PSU placement. IC Role / Device Role / Timing Role: Compact TSSOP package with 4mm × 6.5mm footprint enables local regulation near high-current loads. Use Value: 100% duty cycle operation maintains regulation down to VIN – VOUT < 100mV, extending usable input range in brownout conditions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS543320RTWR | Single 3A channel; requires two units for dual output; 2.2MHz fixed frequency; no phase shift capability. | Lacks native dual-channel integration and interleave control - increases component count and layout complexity. | Choose only if needing separate control per rail or compatibility with TI's WEBENCH ecosystem. |
| MP2451DT-LF-Z | Single 2A channel; 2MHz fixed frequency; no Burst Mode; higher 300µA IQ; no DDR/sink capability. | Not suitable for DDR termination or low-IQ battery operation; limited to simpler, cost-sensitive single-rail designs. | Select only for non-critical, low-performance applications where size and efficiency are secondary. |
Compared with TPS543320RTWR and MP2451DT-LF-Z, the LTC3615EFE-1#TRPBF delivers integrated dual-channel control with phase-shift optimization, 130µA Burst Mode IQ, and DDR-compliant sink capability - making it uniquely suited for space- and efficiency-constrained dual-rail systems.
Availability
LTC3615EFE-1#TRPBF is available at Aetrix Electronics and suitable for point-of-load regulation, DDR memory termination, and portable computer systems requiring stable component supply, full-temperature-range qualification (–40°C to 125°C), and long-term industrial lifecycle support.
Supply support for LTC3615EFE-1#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its precision analog and power management portfolio with rigorous automotive and industrial qualification standards.
The LTC3615EFE-1#TRPBF belongs to Linear's high-efficiency monolithic DC/DC converter family, designed specifically for compact, high-density power delivery in battery-powered and thermally constrained systems.
FAQ
What is the maximum supported switching frequency for LTC3615EFE-1#TRPBF?
The LTC3615EFE-1#TRPBF supports an externally programmable switching frequency up to 4MHz via the RT/SYNC pin - either using a resistor-to-ground or an external clock signal. At 4MHz, it enables use of very small inductors (e.g., 0.47µH) and ceramic capacitors, reducing overall solution size. The internal oscillator defaults to 2.25MHz when RT/SYNC is tied to SVIN.
How does LTC3615EFE-1#TRPBF differ from the standard LTC3615 version?
The LTC3615EFE-1#TRPBF implements the LTC3615-1 variant, which supports 140°/180° phase shift (vs. 0°/90°/180° in LTC3615). This difference is defined by internal logic mapping of the PHASE pin and affects ripple cancellation performance in dual-output configurations. All other electrical specs, pinout, and package are identical.
Can LTC3615EFE-1#TRPBF operate in DDR termination mode?
Yes - the LTC3615EFE-1#TRPBF supports DDR termination mode when the SRLIM pin is tied to SVIN. In this mode, it provides ±1.5A sink/source capability with forced continuous operation, enabling compliant VTT regulation for DDR3/DDR4 memory interfaces while maintaining tight tracking to VDDQ.
What thermal performance can be expected from the TSSOP package of LTC3615EFE-1#TRPBF?
The LTC3615EFE-1#TRPBF in the 24-pin TSSOP (FE) package has a specified θJA of 33°C/W when the exposed PGND pad (Pin 25) is properly soldered to a minimum 1-in² copper plane. Junction temperature rise is calculated as TJ = TA + (PD × 33). Derating is recommended above 125°C junction temperature to ensure long-term reliability.
Does LTC3615EFE-1#TRPBF support power supply sequencing with other rails?
Yes - the TRACK/SS1 and TRACK/SS2 pins enable precise start-up sequencing. By connecting these pins to a reference voltage ramp (e.g., from another regulator's output), the LTC3615EFE-1#TRPBF synchronizes its output rise time and slope, ensuring safe boot sequences for FPGAs, CPUs, and memory subsystems without external timers or supervisors.
LTC3615EFE-1#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.25V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 3A
- Frequency - Switching:
- 400kHz ~ 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
LTC3615EFE-1#TRPBF FAQ
1.How can I place an order for LTC3615EFE-1#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3615EFE-1#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3615EFE-1#TRPBF reliable?
The price and inventory of LTC3615EFE-1#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3615EFE-1#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC3615EFE-1#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3615EFE-1#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3615EFE-1#TRPBF?
LTC3615EFE-1#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3615EFE-1#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3615EFE-1#TRPBF?
For technical support, including LTC3615EFE-1#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3615EFE-1#TRPBF requirements.
6.How does Aetrix verify that LTC3615EFE-1#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC3615EFE-1#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3615EFE-1#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC3615EFE-1#TRPBF?
All LTC3615EFE-1#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3615EFE-1#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3615EFE-1#TRPBF part is unused and in its original packaging.
Return procedure for LTC3615EFE-1#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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