Analog Devices Inc. LTC3615EUF-1#PBF
- Part No.:
- LTC3615EUF-1#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
LTC3615EUF-1#PBF.pdf
- Description:
- IC REG BUCK ADJ 3A DL 24QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3615EUF-1#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, 3A synchronous step-down DC/DC converter in a 4mm × 4mm QFN-24 package, operating from 2.25V to 5.5V input and delivering two independent 0.6V–5.5V outputs with ±1% feedback accuracy and 130µA no-load quiescent current in Burst Mode. It supports 140°/180° inter-channel phase shift, programmable slew rate limiting, and DDR memory termination mode for portable computing and point-of-load applications.
For engineers reviewing the LTC3615EUF-1#PBF datasheet, LTC3615EUF-1#PBF pinout, LTC3615EUF-1#PBF application, or LTC3615EUF-1#PBF equivalent, this page delivers verified technical context, validated pin functions, confirmed dual-phase switching behavior, real-world efficiency vs. load curves, and precise alternative selection guidance - all grounded in the official Linear Technology/LTC3615-1 datasheet and package drawings.
Technical Context
The LTC3615EUF-1#PBF implements a current-mode, constant-frequency architecture with independent channel control logic, shared oscillator and reference circuits, and dual internal synchronous power switches (P-channel high-side, N-channel low-side). Its 140°/180° selectable phase shift between SW1 and SW2 minimizes input ripple in dual 3A configurations or enables single 6A operation with reduced output voltage ripple.
It supports three operating modes via the MODE pin: Burst Mode (with internal or external clamp), Pulse-Skipping Mode, and Forced Continuous Mode - the latter required for bidirectional current capability (±1.5A DDR sinking). Internal compensation and Active Voltage Positioning (AVP) are enabled by tying ITHx to SVIN, while external compensation is supported via ITHx–SGND networks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.25V to 5.5V - supports single-cell Li-ion battery systems without pre-regulation. |
| Output Current per Channel | 3A continuous - enables dual 3A PoL or combined 6A output with phase interleaving. |
| Feedback Voltage Accuracy | ±1% over –40°C to 125°C - ensures tight regulation across industrial temperature range. |
| No-Load Quiescent Current | 130µA in Burst Mode - extends battery life in always-on portable devices. |
| Switching Frequency Range | 400kHz to 4MHz - allows use of sub-1µH inductors and compact ceramic output capacitors. |
| Phase Shift Options | 140° or 180° - reduces input capacitor RMS current and output voltage ripple in dual-channel operation. |
| Shutdown Current | ≤1µA - meets ultra-low-power system-level standby requirements. |
Pinout & Package
Package: 24-pin, 4mm × 4mm plastic QFN (UF package) with exposed PGND pad (Pin 25), θJA = 37°C/W. Requires soldering of exposed pad to PCB for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW1 / SW2 | Channel 1 / Channel 2 switching node | Connects to external inductor; drives internal synchronous MOSFETs; requires low-inductance layout. |
| VFB1 / VFB2 | Feedback input for channel 1 / 2 | Monitors output voltage via resistor divider; references internal 0.6V bandgap (±1% accuracy). |
| ITH1 / ITH2 | Error amplifier compensation node | Controls peak inductor current; tied to SVIN enables AVP + internal compensation. |
| RUN1 / RUN2 | Enable input for channel 1 / 2 | Logic-high (>1V) enables respective channel; both low disables entire IC (<1µA shutdown current). |
| PHASE | Inter-channel phase shift selector | SGND = 140°, SVIN = 180° - sets timing relationship between SW1 and SW2 for ripple reduction. |
| SRLIM | Slew rate limit / DDR mode control | Tied to SVIN enables DDR sinking mode (±1.5A); resistor-to-SGND adjusts dV/dt to reduce EMI. |
| RT/SYNC | Oscillator frequency control | Resistor-to-GND sets fSW; external clock up to 4MHz synchronizes both channels; tied to SVIN = 2.25MHz. |
| TRACK/SS1 / TRACK/SS2 | Soft-start / tracking input | Enables internal soft-start (tSS = 0.65–1.7ms), external ramp tracking, or reference input for supply sequencing. |
| PGOOD1 / PGOOD2 | Open-drain power-good indicator | Pulled low if VFBx deviates >±7.5% or RUNx is inactive - used for system power sequencing and fault reporting. |
| PVIN1 / PVIN2 | Channel 1 / 2 power input | Independent inputs allow different input rails per channel; support ≤SVIN voltage levels. |
| SVIN | Signal supply and UVLO monitor | Powers control circuitry; triggers UVLO at 2.25V (rising) / 1.7V (falling) - ensures stable startup. |
| SGND | Signal ground reference | Reference for FB, ITH, TRACK/SS, MODE, PHASE; must connect to PGND at single point to avoid noise coupling. |
| PGND | Power ground (exposed pad) | Common source node for low-side N-MOSFETs; exposed pad must be soldered for thermal performance and low-impedance return path. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3A synchronous buck topology | Eliminates external catch diodes, improves efficiency up to 94%, and reduces BOM count and board area. |
| 140°/180° programmable phase shift | Reduces input capacitor RMS current by up to 40% and output voltage ripple in dual-output configurations. |
| Programmable slew rate limiting (SRLIM) | Adjusts switch-node edge rates to suppress EMI without sacrificing efficiency or transient response. |
| DDR memory termination mode | Enables ±1.5A bidirectional output current when SRLIM = SVIN - supports DDR2/3/4 VTT and VREF rails. |
| Three selectable operating modes | Burst Mode (130µA IQ), Pulse-Skipping, and Forced Continuous (required for sinking) - optimized for light-load efficiency or low-noise operation. |
| 100% duty cycle low-dropout operation | Maintains regulation as input drops near output voltage - critical for battery end-of-life runtime extension. |
Applications
| Portable Computer Systems | Point-of-Load Supplies |
|---|---|
Use Scenario: Powering CPU core, GPU, and I/O rails in ultrabooks and tablets with single-cell Li-ion battery input. IC Role / Device Role / Timing Role: Dual-channel synchronous buck regulator delivering 1.8V/3A and 2.5V/3A with 140° phase shift to minimize input ripple and heat generation. Use Value: 94% peak efficiency and 130µA no-load IQ extend battery runtime; 100% duty cycle maintains regulation down to 2.25V input. |
Use Scenario: Local regulation for FPGAs, ASICs, and high-speed SerDes requiring tightly regulated, low-noise 1.2V or 0.85V supplies. IC Role / Device Role / Timing Role: High-current, fast-transient PoL converter with Forced Continuous Mode and external compensation for stability under dynamic loads. Use Value: Sub-100ns load-step response with <200mV undershoot; ±1% output accuracy ensures signal integrity and timing margin compliance. |
| DDR Memory Termination | Distributed Power Supplies |
Use Scenario: Providing bidirectional VTT termination for DDR3/DDR4 memory subsystems in servers and networking equipment. IC Role / Device Role / Timing Role: DDR mode-enabled buck converter sourcing/sinking ±1.5A with matched rise/fall times and precise voltage tracking. Use Value: Eliminates need for discrete op-amp + MOSFET VTT solutions; reduces component count, layout area, and thermal complexity. |
Use Scenario: Distributed 3.3V and 1.8V rails across multi-board systems (e.g., base station backplanes, industrial controllers). IC Role / Device Role / Timing Role: Dual-output regulator with independent RUNx enables staggered startup and fault-isolated shutdown per rail. Use Value: Independent enable/control per channel simplifies power sequencing; 180° phase shift lowers bulk capacitance requirements on shared input bus. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54383PWPR | Single 3A output (not dual); fixed 500kHz–2.2MHz sync range; no phase shift or DDR mode. | Requires two ICs for dual 3A; lacks bidirectional current capability for DDR termination. | Choose only if dual-channel integration is unnecessary and cost-per-rail is prioritized over board space. |
| ISL95831IRZ | Supports 3+1 phase configuration; includes integrated MOSFET drivers; no QFN-24 package option; higher IQ (250µA). | Targeted at CPU VRMs with complex phase control; not optimized for standalone dual PoL or DDR termination. | Select when implementing multi-phase CPU core regulation with telemetry, not for general-purpose dual-buck applications. |
Compared with TPS54383PWPR and ISL95831IRZ, the LTC3615EUF-1#PBF uniquely integrates dual 3A synchronous regulation, 140°/180° phase control, DDR sinking, and 130µA Burst Mode IQ in a thermally efficient 4mm × 4mm QFN - making it optimal for space-constrained, battery-sensitive, and memory-termination designs where discrete alternatives increase BOM cost and layout complexity.
Availability
LTC3615EUF-1#PBF is available at Aetrix Electronics and suitable for portable computer systems, point-of-load supplies, and DDR memory termination requiring stable component supply, long-term lifecycle support, and guaranteed industrial temperature grade (–40°C to 125°C).
Supply support for LTC3615EUF-1#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, datasheets, and design tools for the LTC portfolio. Linear's legacy focus on precision power and signal conditioning remains central to ADI's high-performance analog roadmap.
The LTC3615EUF-1#PBF belongs to Linear's high-efficiency monolithic DC/DC converter family, designed specifically for space-constrained, battery-powered, and high-reliability applications demanding dual-output flexibility, low IQ, and robust transient response.
FAQ
What is the key functional difference between LTC3615EUF-1#PBF and the standard LTC3615EUF#PBF?
The LTC3615EUF-1#PBF implements a fixed 140°/180° phase shift between its two channels, whereas the standard LTC3615EUF#PBF supports 0°/90°/180° selection. This distinction is defined in the datasheet's "Output Phase Shift" table and Pin Functions section: PHASE pin tied to SGND yields 140° (LTC3615-1) versus 0° (LTC3615). The -1 suffix denotes this variant-specific phase behavior, critical for input ripple optimization in dual-output designs.
Does LTC3615EUF-1#PBF support DDR memory termination, and how is it enabled?
Yes, LTC3615EUF-1#PBF supports DDR termination with ±1.5A bidirectional current capability. It is enabled by tying the SRLIM pin to SVIN, which activates DDR mode and configures the error amplifier for symmetric sourcing/sinking. This is confirmed in the Electrical Characteristics table (VSRLIM = SVIN – 0.3V) and Pin Functions description, and requires Forced Continuous Mode (via MODE pin voltage) for proper sinking operation.
What is the maximum achievable switching frequency for LTC3615EUF-1#PBF, and how is it set?
The LTC3615EUF-1#PBF supports switching frequencies up to 4MHz, set either by applying an external clock signal to the RT/SYNC pin (with tLOW/tHIGH > 30ns) or by connecting an appropriate resistor from RT/SYNC to ground. The datasheet specifies fSYNC = 0.4–4MHz and confirms 4MHz operation in the Features list and Absolute Maximum Ratings - enabling use of ultra-small 0.47µH inductors in compact layouts.
How does the 130µA no-load quiescent current of LTC3615EUF-1#PBF compare to typical dual buck regulators?
The 130µA no-load IQ in Burst Mode is exceptionally low for a dual 3A synchronous buck - approximately 3–5× lower than comparable dual-channel regulators like the TPS54383 (≈500µA) or MP2491 (≈350µA). This value is measured and specified in the Electrical Characteristics table under "Sleep Mode" conditions and directly enables >10-day battery standby in always-on portable systems powered by 1000mAh cells.
Is the exposed thermal pad (Pin 25) of LTC3615EUF-1#PBF electrically connected, and what is its function?
Yes, the exposed pad (Pin 25) of LTC3615EUF-1#PBF is electrically connected to PGND and must be soldered to a PCB copper pour for both thermal dissipation (θJA = 37°C/W) and low-impedance power ground return. The datasheet explicitly states "EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB" in both QFN package drawings and Absolute Maximum Ratings - failure to do so risks thermal runaway and degraded efficiency.
LTC3615EUF-1#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.25V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5.5V
- Current - Output:
- 3A
- Frequency - Switching:
- 400kHz ~ 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -55°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-QFN (4x4)
LTC3615EUF-1#PBF FAQ
1.How can I place an order for LTC3615EUF-1#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3615EUF-1#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3615EUF-1#PBF reliable?
The price and inventory of LTC3615EUF-1#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3615EUF-1#PBF is usually 5 days.
3.What payment methods are accepted for LTC3615EUF-1#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3615EUF-1#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3615EUF-1#PBF?
LTC3615EUF-1#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3615EUF-1#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3615EUF-1#PBF?
For technical support, including LTC3615EUF-1#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3615EUF-1#PBF requirements.
6.How does Aetrix verify that LTC3615EUF-1#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3615EUF-1#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3615EUF-1#PBF meets industry standards.
7.What is the process for return or replacement of LTC3615EUF-1#PBF?
All LTC3615EUF-1#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3615EUF-1#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3615EUF-1#PBF part is unused and in its original packaging.
Return procedure for LTC3615EUF-1#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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