Analog Devices Inc. LTC3618IUF#PBF
- Part No.:
- LTC3618IUF#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
LTC3618IUF#PBF.pdf
- Description:
- IC REG CONV DDR 2OUT 24QFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,416
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Product details
Overview
LTC3618IUF#PBF from Analog Devices (formerly Linear Technology) is a dual-channel synchronous buck converter IC designed specifically for DDR memory termination and reference voltage generation. It delivers ±3A per channel at up to 4MHz switching frequency, supports 2.25V–5.5V input, achieves ±1% VDDQ output accuracy, and generates VTTR = VDDQIN/2 with ±10mA drive capability - enabling full DDR, DDR2, and DDR3 compliant power delivery in compact systems.
For engineers reviewing the LTC3618IUF#PBF datasheet, LTC3618IUF#PBF pinout, LTC3618IUF#PBF application, or LTC3618IUF#PBF equivalent, key selection criteria include dual ±3A sourcing/sinking capability, programmable 0°/90°/180° inter-channel phase shift, internal/external soft-start control for VDDQ and VTT, ±1% output voltage accuracy over temperature, and support for forced continuous or pulse-skipping mode on VDDQ.
Technical Context
The LTC3618IUF#PBF implements a current-mode, constant-frequency architecture with independent control loops for VDDQ and VTT outputs. Its VDDQ regulator uses an internal 0.6V reference and external feedback divider, while VTT regulation is tied directly to VTTR (VDDQIN/2), eliminating need for separate reference circuitry. Both channels feature peak-current limiting, slope compensation, and overvoltage/undervoltage protection.
Phase shift between SW1 and SW2 is digitally selected via the PHASE pin (0° at SGND, 90° at mid-rail, 180° at SVIN), reducing input ripple without external synchronization. The MODE/SYNC pin enables either pulse-skipping mode (for light-load efficiency) or forced continuous mode (required for sinking current) on VDDQ only; VTT operates exclusively in forced continuous mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.25V to 5.5V - supports wide range of intermediate bus rails including 3.3V and 5V supplies. |
| VDDQ Output Accuracy | ±1% over –40°C to 125°C - ensures stable DDR memory interface voltage under thermal stress. |
| VTT Output Capability | ±3A sourcing/sinking - meets DDR termination current requirements for high-speed bidirectional signaling. |
| Switching Frequency | Programmable up to 4MHz via RT resistor or external clock - enables use of sub-1µH inductors and compact layouts. |
| VTTR Output | VDDQIN/2 with ±10mA drive - provides buffered, low-noise DDR reference voltage without external op-amp. |
| Shutdown Current | ≤1µA - minimizes system standby power in battery-backed or always-on applications. |
| Package | 24-pin 4mm × 4mm QFN (UF) with exposed PGND pad - optimized for thermal performance in high-current DC/DC designs. |
Pinout & Package
Package: 24-lead (4mm × 4mm) plastic QFN (UF) with exposed thermal pad (Pin 25 = PGND). Requires soldering of exposed pad to PCB for electrical continuity and thermal management (θJA = 46.9°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| FB1 | VDDQ Feedback Input | Connects to resistive divider across VDDQ output; regulates VDDQ to 0.6V reference with ±1% accuracy. |
| ITH1 | VDDQ Error Amplifier Compensation | Accepts external RC network for loop stability tuning; tied to SVIN for internal compensation. |
| TRACK/SS1 | VDDQ Soft-Start / Tracking Control | Configures internal soft-start (tied to SVIN), external soft-start (RC network), or supply tracking behavior. |
| PHASE | Inter-Channel Phase Selection | SGND = 0°, mid-rail = 90°, SVIN = 180° - reduces input ripple by staggering SW1/SW2 switching edges. |
| VTTR | DDR Reference Buffer Output | Delivers VDDQIN/2 with ±10mA drive; must be loaded ≤0.1µF for stability; enabled/disabled with RUN2. |
| PGOOD1 / PGOOD2 | Open-Drain Power-Good Indicators | Assert low if respective output deviates >±8% from setpoint or RUNx is inactive - enables system sequencing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual ±3A Synchronous Buck Outputs | Enables single-chip DDR termination (VTT) and core supply (VDDQ) with bidirectional current handling for write/read cycles. |
| Selectable Inter-Channel Phase Shift | 0°, 90°, or 180° alignment between SW1 and SW2 minimizes input capacitor RMS current and reduces EMI filtering burden. |
| VDDQ Pulse-Skipping or Forced Continuous Mode | MODE/SYNC pin selects light-load efficiency (pulse-skipping) or mandatory sinking operation (forced continuous) - no external mode logic required. |
| Integrated VTTR Buffer | Eliminates discrete op-amp and resistor network for DDR reference; maintains VDDQIN/2 accuracy with ±10mA load capability. |
| Internal/External Soft-Start for VDDQ | TRACK/SS1 pin supports fixed-timing internal soft-start (tSOFT-START1 = 0.5–2ms) or user-programmed ramp for inrush control. |
| Robust Protection Suite | Includes undervoltage lockout (UVLO), overvoltage lockout (OVLO), short-circuit foldback, and thermal shutdown - prevents damage during fault conditions. |
Applications
| DDR Memory Power Delivery | DDR2/DDR3 Termination Supply |
|---|---|
|
Use Scenario: Providing regulated VDDQ (1.8V) and matched VTT (0.9V) for DDR2/DDR3 SDRAM modules in servers and networking equipment. IC Role / Device Role / Timing Role: Dual-output buck controller generating tightly tracked DDR supply and termination voltages with synchronized switching. Use Value: Eliminates need for two discrete regulators and external reference buffer; ±1% VDDQ accuracy ensures signal integrity at data rates up to 800MT/s. |
Use Scenario: Delivering bidirectional ±3A termination current for DDR3 LRDIMM modules requiring dynamic VTT sourcing and sinking during read/write transitions. IC Role / Device Role / Timing Role: High-current synchronous buck regulator operating in forced continuous mode to maintain VTT regulation under reverse current conditions. Use Value: Full ±3A sinking capability avoids external FETs or diodes; 180° phase shift reduces input ripple by ~70% versus in-phase operation. |
| Tracking Power Supplies | Low-Profile DDR Reference Generation |
|
Use Scenario: Generating VTT that tracks VDDQIN in systems where VDDQ is derived from a separate upstream regulator. IC Role / Device Role / Timing Role: Uses VDDQIN as direct reference input to generate VTTR = VDDQIN/2, then regulates VTT to VTTR via FB2. Use Value: Enables precise tracking without external error amplifier; eliminates drift-induced timing skew between VDDQ and VTT rails. |
Use Scenario: Replacing discrete op-amp + resistor networks for DDR reference voltage generation in space-constrained embedded controllers. IC Role / Device Role / Timing Role: Integrated VTTR buffer delivering VDDQIN/2 with ±10mA drive and <0.1µF capacitive load stability. Use Value: Reduces BOM count by 4 components; 0.5% VTTR accuracy over temperature maintains DDR setup/hold margins. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-output DDR power supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51220ARUKT | Single-channel VDDQ + integrated VTT driver (not full ±3A buck); max 2.5A VTT sink; no VTTR buffer; 3mm × 3mm QFN-16 | Limited to DDR3 LVDIMMs with lower VTT current demand; lacks independent VTT regulation and VTTR buffering | Choose when board space is critical and VTT current ≤2.5A; avoid for DDR2 or high-current DDR3 applications. |
| ISL95812IRZ | Dual 3A buck with integrated MOSFETs; supports 0°/180° phase; no VTTR buffer; requires external VREF for VTT; 5mm × 5mm QFN-32 | Needs external 0.5×VDDQ reference and compensation; higher pin count; no built-in VTTR drive capability | Prefer when design already includes precision reference circuitry and thermal budget allows larger package. |
Compared with TPS51220ARUKT and ISL95812IRZ, the LTC3618IUF#PBF uniquely integrates a ±10mA VTTR buffer, supports full ±3A bidirectional VTT current, and delivers ±1% VDDQ accuracy without external components - making it optimal for space-constrained, high-reliability DDR2/DDR3 systems requiring minimal BOM and guaranteed tracking.
Availability
LTC3618IUF#PBF is available at Aetrix Electronics and suitable for DDR memory power delivery, DDR2/DDR3 termination supplies, tracking power supplies, low-profile DDR reference generation, and high-current bidirectional termination applications requiring stable component supply and long-term industrial availability.
Supply support for LTC3618IUF#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, serving industrial, automotive, communications, and computing markets.
The LTC3618IUF#PBF belongs to Linear's high-efficiency monolithic DC/DC converter product line, engineered specifically for DDR memory subsystems requiring tightly coupled VDDQ/VTT rails, low-noise reference generation, and robust transient response in compact form factors.
FAQ
What is the maximum supported switching frequency for the LTC3618IUF#PBF?
The LTC3618IUF#PBF supports switching frequencies up to 4MHz, either via external resistor on the RT pin or synchronization to an external clock applied to the MODE/SYNC pin. At 4MHz, minimum on-time (80ns) limits practical duty cycle to ≥32% for 5V input, requiring careful inductor selection to maintain regulation under low-VIN conditions.
Does the LTC3618IUF#PBF support sinking current on the VTT output?
Yes, the LTC3618IUF#PBF supports full ±3A bidirectional current on the VTT output, but only when operating in forced continuous mode - which is the default and only operational mode for VTT. This enables true DDR termination for both read (sourcing) and write (sinking) cycles without external components.
How is VTTR generated and what is its load capability in the LTC3618IUF#PBF?
In the LTC3618IUF#PBF, VTTR is generated by an internal high-accuracy op-amp buffer that outputs exactly VDDQIN/2. It delivers ±10mA with stability up to 0.1µF capacitive load, and is enabled or disabled synchronously with RUN2. VTTR serves as both the reference for VTT regulation and the DDR reference voltage.
Can the LTC3618IUF#PBF operate with different input voltages on PVIN1 and PVIN2?
Yes, the LTC3618IUF#PBF supports independent power inputs: PVIN1 supplies the VDDQ channel and PVIN2 supplies the VTT channel. They may be connected to equal or different supplies (e.g., 3.3V for VDDQ and 5V for VTT), as long as both remain within the 2.25V–5.5V operating range and do not exceed absolute maximum ratings (–0.3V to 6V).
What thermal considerations apply to the LTC3618IUF#PBF in QFN-24 (UF) package?
The LTC3618IUF#PBF in 4mm × 4mm QFN-24 (UF) package has θJA = 46.9°C/W. The exposed PGND pad (Pin 25) must be soldered to a thermally robust PCB copper area to achieve rated thermal performance. Under full ±3A load at 5.5V input, junction temperature rise can exceed 60°C - thermal design must ensure TJ remains ≤125°C under worst-case ambient and airflow conditions.
LTC3618IUF#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Converter, DDR
- Voltage - Input:
- 2.25V ~ 5.5V
- Number of Outputs:
- 2
- Voltage - Output:
- Adj to 0.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-QFN (4x4)
LTC3618IUF#PBF FAQ
1.How can I place an order for LTC3618IUF#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3618IUF#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3618IUF#PBF reliable?
The price and inventory of LTC3618IUF#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3618IUF#PBF is usually 5 days.
3.What payment methods are accepted for LTC3618IUF#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3618IUF#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3618IUF#PBF?
LTC3618IUF#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3618IUF#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3618IUF#PBF?
For technical support, including LTC3618IUF#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3618IUF#PBF requirements.
6.How does Aetrix verify that LTC3618IUF#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3618IUF#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3618IUF#PBF meets industry standards.
7.What is the process for return or replacement of LTC3618IUF#PBF?
All LTC3618IUF#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3618IUF#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3618IUF#PBF part is unused and in its original packaging.
Return procedure for LTC3618IUF#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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