Analog Devices Inc. LTC3619BEDD#PBF
- Part No.:
- LTC3619BEDD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 10-WFDFN Exposed Pad
- Datasheet:
-
LTC3619BEDD#PBF.pdf
- Description:
- IC REG BUCK ADJ DL 10DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3619BEDD#PBF from Analog Devices (formerly Linear Technology) is a dual monolithic synchronous buck regulator with constant-frequency current-mode control, delivering 400mA on Channel 1 and 800mA on Channel 2 across 2.5V–5.5V input. It features programmable average input current limiting (±5% accuracy), 2.25MHz switching, 0.6V feedback reference, and independent soft-start-ideal for USB-powered handheld devices requiring stable dual-rail power under pulsed loads.
For engineers reviewing the LTC3619BEDD#PBF datasheet, LTC3619BEDD#PBF pinout, LTC3619BEDD#PBF application, or LTC3619BEDD#PBF equivalent, key selection criteria include its 10-lead 3mm × 3mm DFN package, channel-specific power-good monitoring, 100% duty-cycle dropout operation, and precise input current limit programming via RLIM pin.
Technical Context
The LTC3619BEDD#PBF implements two independent current-mode buck regulators sharing a synchronized 2.25MHz clock. Each channel uses internal P-channel and N-channel MOSFETs with RDS(ON) of 0.45Ω/0.35Ω (Ch1) and 0.27Ω/0.25Ω (Ch2) at 5V, enabling high efficiency up to 96%. The device continuously monitors summed input current and enforces the programmed limit by reducing Channel 2's peak inductor current while maintaining Channel 1 regulation.
Light-load operation transitions to low-noise pulse-skipping mode, preserving output voltage accuracy (±2%) and minimizing RF interference. Soft-start ramps each output over ~950µs, and short-circuit protection forces extended bottom-switch conduction to prevent inductor current runaway without latch-off.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.5V to 5.5V - supports single-cell Li-ion and USB 2.0/3.0 bus power without external LDO pre-regulation. |
| Output Current (Ch1 / Ch2) | 400mA / 800mA - enables independent powering of core logic and I/O rails in space-constrained portable systems. |
| Switching Frequency | 2.25MHz (typ) - allows use of compact 1.5µH–4.7µH surface-mount inductors and reduces output capacitor size. |
| Feedback Reference | 0.6V ±2% - sets minimum output voltage and enables precise scaling down to 0.6V with external resistor dividers. |
| Input Current Limit Accuracy | ±5% - ensures reliable USB port compliance and prevents host supply collapse during GSM pulse loads. |
| Shutdown Current | ≤1µA - minimizes battery drain in always-on standby modes for IoT edge sensors and wearables. |
| Thermal Resistance θJA | 40°C/W - achieved via exposed GND pad soldered to PCB; supports 800mA continuous output at 85°C ambient. |
Pinout & Package
The LTC3619BEDD#PBF is housed in a thermally enhanced 10-lead 3mm × 3mm plastic DFN package with an exposed GND pad (Pin 11) that must be soldered to the PCB for thermal and electrical integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VFB1 (Pin 1) | Channel 1 feedback input | Connects to resistor divider on Ch1 output; regulates VOUT1 to 0.6V reference with ±2% accuracy. |
| RUN1 (Pin 2) | Channel 1 enable control | Logic-high (>0.4V) enables Ch1; logic-low (<0.1V) shuts down Ch1 with ≤1µA quiescent current. |
| RLIM (Pin 3) | Average input current limit set | Resistor-to-GND programs limit (e.g., 116kΩ = 475mA); capacitor filters transient response. |
| PGOOD1 (Pin 4) | Channel 1 power-good flag | Open-drain output pulled low if VFB1 deviates >±5% from 0.6V; blanked for 90µs during startup. |
| SW1 (Pin 5) | Channel 1 switch node | Connects to inductor; swings between VIN and GND; requires low-ESR ceramic decoupling near pin. |
| VIN (Pin 6) | Main power input | Supplies both channels; must be decoupled with ≥10µF ceramic capacitor placed adjacent to pin. |
| SW2 (Pin 7) | Channel 2 switch node | Independent switch node for Ch2; shares VIN rail but requires separate inductor and output filter. |
| PGOOD2 (Pin 8) | Channel 2 power-good flag | Functionally identical to PGOOD1 but monitors VFB2; enables sequencing or fault isolation in dual-rail systems. |
| RUN2 (Pin 9) | Channel 2 enable control | Independent enable for Ch2; allows staggered startup or dynamic rail disabling without affecting Ch1. |
| VFB2 (Pin 10) | Channel 2 feedback input | Same function as VFB1 but for Ch2; supports different output voltages (e.g., 1.8V + 3.3V) simultaneously. |
| GND (Pin 11) | Power and signal ground | Exposed thermal pad; must be soldered to large PCB copper area for thermal dissipation and noise reduction. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable average input current limit | Enables USB-compliant designs: RLIM resistor sets limit from 200mA to peak switch current, with ±5% tolerance over temperature. |
| Dual independent soft-start | Each channel ramps output over ~950µs when RUNx is asserted, preventing inrush into large output capacitors (e.g., supercapacitors). |
| 100% duty-cycle operation | Maintains regulation down to VOUT = VIN − (IOUT × RDS(ON)), extending battery runtime in low-VIN dropout conditions. |
| Pulse-skipping light-load mode | Reduces audible noise and EMI while sustaining ±2% output accuracy at loads <10mA per channel. |
| Short-circuit protected outputs | Prevents thermal runaway during output shorts by forcing extended N-FET conduction to safely discharge inductor energy. |
Applications
| USB-Powered Portable Devices | Radio Transmitters (GSM Pulse Load) |
|---|---|
Use Scenario: Powering dual-rail subsystems (e.g., 1.8V SoC core + 3.3V RF front-end) from a single USB 5V source with strict 500mA host port compliance. IC Role / Device Role / Timing Role: Dual synchronous buck regulator providing isolated, current-limited DC/DC conversion with real-time input current monitoring. Use Value: Prevents USB host voltage droop during burst transmission by enforcing 475mA average input limit while delivering 800mA peak to RF stage. | Use Scenario: Supplying GSM/GPRS transceivers requiring high-current 577µs pulses at 4.7ms intervals, where input supply has limited current capacity. IC Role / Device Role / Timing Role: Dual-output PMIC with programmable CLIM capacitor to tune input current limit response time to match pulse duration. Use Value: Using 2.2nF CLIM achieves 92µs limit activation-enabling full 2A pulse delivery before current limiting engages, preserving RF transmit integrity. |
| Supercapacitor Charging Systems | Handheld Medical Sensors |
Use Scenario: Charging a 2.2mF supercapacitor bank from USB while simultaneously powering a 3.4V/800mA load (e.g., display backlight). IC Role / Device Role / Timing Role: Dual buck controller with Channel 2 delivering regulated 3.4V/800mA and Channel 1 managing charging current into supercap bank. Use Value: Independent RUN2 control allows dynamic load shedding during supercap charge cycles; 100% duty cycle sustains output as input drops below 3.4V. | Use Scenario: Long-life battery-powered wearable sensor with ultra-low shutdown current and precision analog rail requirements (e.g., 1.2V ADC reference + 3.3V MCU). IC Role / Device Role / Timing Role: Dual low-noise buck regulator supporting burst-mode operation and ±2% output accuracy across –40°C to 125°C. Use Value: ≤1µA shutdown current extends coin-cell life; pulse-skipping mode eliminates audible coil whine critical for patient comfort. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3619EMSE#PBF | Same silicon, 10-lead MSOP package (θJA = 45°C/W); larger footprint, no exposed thermal pad. | Suitable for prototyping or lower-power applications where DFN reflow is not available; less efficient thermal performance. | Select when board assembly process lacks DFN capability or when manual rework is required. |
| TPS62150ARGTR | Single 1A buck (not dual); 2.5V–6V input; fixed 1.2V/1.5V/1.8V/2.5V/3.3V options; no programmable input current limit. | Requires two ICs to replicate dual-rail functionality; lacks USB input current enforcement and independent channel enable. | Choose only for single-rail designs where cost-per-amp is prioritized over feature integration. |
Compared with LTC3619EMSE#PBF, the LTC3619BEDD#PBF offers superior thermal performance and smaller footprint due to its exposed-pad DFN; compared with TPS62150ARGTR, it provides true dual-channel integration with USB-compliant input current limiting-eliminating design complexity and component count in portable dual-rail systems.
Availability
LTC3619BEDD#PBF is available at Aetrix Electronics and suitable for USB-powered portable devices, GSM radio transmitters, supercapacitor charging systems, and handheld medical sensors requiring stable component supply across industrial temperature ranges.
Supply support for LTC3619BEDD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its legacy of high-performance power management ICs with rigorous automotive and industrial qualification.
The LTC3619B product line delivers dual synchronous buck regulation with programmable input current limiting for space-constrained, battery-operated systems demanding USB compliance and pulsed-load resilience.
FAQ
What is the operating temperature range for the LTC3619BEDD#PBF?
The LTC3619BEDD#PBF is specified for operation from –40°C to 125°C junction temperature. Its DFN package with exposed GND pad achieves θJA = 40°C/W, enabling full 800mA Channel 2 output at 85°C ambient with proper PCB copper area. The part is tested and guaranteed over this full range per its data sheet specifications.
How do I program the input current limit on the LTC3619BEDD#PBF?
Connect a resistor (e.g., 116kΩ for 475mA) between the RLIM pin (Pin 3) and GND. The LTC3619BEDD#PBF uses internal current sensing to sum both channels' input currents; when the RLIM voltage reaches 1V, Channel 2 is current-limited. Add a CLIM capacitor (≥100pF) from RLIM to GND to filter transients-the value determines response time (e.g., 2.2nF yields ~92µs delay).
Does the LTC3619BEDD#PBF support independent power sequencing between channels?
Yes. The LTC3619BEDD#PBF provides separate RUN1 (Pin 2) and RUN2 (Pin 9) inputs, allowing independent enable/disable control of each channel. This enables flexible power-up/down sequencing-for example, asserting RUN1 first to stabilize a core rail before enabling RUN2 for I/O, or shutting down Channel 2 during low-power sleep while keeping Channel 1 active.
What is the purpose of the exposed pad on the LTC3619BEDD#PBF DFN package?
The exposed pad (Pin 11) on the LTC3619BEDD#PBF is electrically and thermally connected to GND. It must be soldered to a dedicated PCB copper pour to achieve the specified θJA = 40°C/W and ensure safe operation at full load. Failure to connect it degrades thermal performance and may cause premature thermal shutdown or reduced reliability.
Can the LTC3619BEDD#PBF operate with a 2.5V input voltage?
Yes. The LTC3619BEDD#PBF operates down to 2.5V input, supporting single-cell Li-ion batteries. At low VIN, 100% duty cycle operation maintains regulation-e.g., delivering 1.8V at 400mA with VIN as low as ~2.0V (accounting for RDS(ON) drop). Efficiency remains >85% at 2.5V input/1.8V output/100mA load per channel in pulse-skipping mode.
LTC3619BEDD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 10-WFDFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5.5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 5V
- Current - Output:
- 400mA, 800mA
- Frequency - Switching:
- 2.25MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 10-DFN (3x3)
LTC3619BEDD#PBF FAQ
1.How can I place an order for LTC3619BEDD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3619BEDD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3619BEDD#PBF reliable?
The price and inventory of LTC3619BEDD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3619BEDD#PBF is usually 5 days.
3.What payment methods are accepted for LTC3619BEDD#PBF?
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4.How is shipping managed for LTC3619BEDD#PBF?
LTC3619BEDD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3619BEDD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3619BEDD#PBF?
For technical support, including LTC3619BEDD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3619BEDD#PBF requirements.
6.How does Aetrix verify that LTC3619BEDD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3619BEDD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3619BEDD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3619BEDD#PBF?
All LTC3619BEDD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3619BEDD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3619BEDD#PBF part is unused and in its original packaging.
Return procedure for LTC3619BEDD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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