Analog Devices Inc. LTC3633AEUFD#PBF
- Part No.:
- LTC3633AEUFD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC3633AEUFD#PBF.pdf
- Description:
- IC REG BUCK ADJ 3A DL 28QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3633AEUFD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel monolithic synchronous step-down regulator with controlled on-time current mode architecture, delivering 3A per channel across 3.6V–20V input and supporting 0.6V–6V output voltage range. It features phase-selectable operation (0°/180°), 500kHz–4MHz adjustable switching frequency, and integrated power-good status outputs for point-of-load power delivery in battery-powered instruments and distributed systems.
For engineers reviewing the LTC3633AEUFD#PBF datasheet, LTC3633AEUFD#PBF pinout, LTC3633AEUFD#PBF application, or LTC3633AEUFD#PBF equivalent, key selection criteria include its dual 3A output capability, 180° interleaved phase support to reduce input ripple, Burst Mode® vs forced continuous mode trade-offs, and QFN-28 (4mm × 5mm) thermal performance with exposed PGND pad.
Technical Context
The LTC3633AEUFD#PBF implements a constant-frequency controlled on-time architecture synchronized via internal PLL to either an external clock or programmable RT resistor. Its two independent buck channels share no internal coupling except for shared INTVCC and V2P5 rails, enabling flexible dual-output or parallel configurations.
Each channel uses valley-current sensing with user-adjustable ITH threshold, 0.6V reference with ±1% accuracy over temperature, and dedicated RUN/PGOOD/TRACKSS pins for sequencing and monitoring. Phase shift is controlled solely by PHMODE logic level, not by timing skew or external delay elements.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.6V to 20V - supports single Li-ion stack (up to 4S) and standard 12V/5V intermediate bus rails |
| Output Current per Channel | 3A continuous - enables compact dual-rail POL without external MOSFETs or controllers |
| Switching Frequency Range | 500kHz to 4MHz - allows optimization between small magnetics (high-freq) and efficiency (low-freq) |
| Feedback Reference Voltage | 0.6V ±1% - enables low-VOUT regulation down to 0.6V with standard resistor dividers |
| Efficiency | Up to 95% at full load - achieved via low RDS(ON) (130mΩ top / 65mΩ bottom) and optimized gate drive |
| Phase Shift Control | Selectable 0° or 180° - reduces RMS input current and eases input capacitor sizing when interleaved |
| Protection Features | Input overvoltage lockout (22.5V trip), overtemperature shutdown, short-circuit protection - ensures robust operation under fault conditions |
Pinout & Package
Package: 28-lead (4mm × 5mm) plastic QFN with exposed PGND pad (Pin 29), rated for –40°C to +125°C junction temperature (θJA = 43°C/W).
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| PGOOD1 (Pin 1) | Channel 1 power-good status output | Open-drain signal pulled low if VFB1 deviates >±8% from 0.6V; releases at ±5% with 40µs filter |
| PHMODE (Pin 2) | Phase select control input | Logic high → 180° out-of-phase operation; logic low → in-phase; must not float |
| RUN1 (Pin 3) | Channel 1 enable input | Active-high enable with 1.22V threshold; <1V disables channel 1 and shuts down associated power stage |
| MODE/SYNC (Pin 4) | Mode selection & sync input | Ground → forced continuous mode; INTVCC or floating → Burst Mode®; external clock → synchronization |
| RT (Pin 5) | Oscillator frequency programming | Resistor-to-SGND sets fSW from 500kHz–4MHz; tied to INTVCC → ~2MHz default |
| RUN2 (Pin 6) | Channel 2 enable input | Identical function to RUN1 but for second channel; independent control enables staggered startup |
| SGND (Pin 7) | Signal ground reference | Low-noise analog ground for feedback divider, RT, and compensation networks; separate from PGND |
| PGOOD2 (Pin 8) | Channel 2 power-good status output | Functionally identical to PGOOD1 but for VFB2; enables independent rail monitoring |
| VFB2 (Pin 9) | Channel 2 feedback input | Connects to resistor divider; error amplifier compares to 0.6V reference to regulate VOUT2 |
| TRACKSS2 (Pin 10) | Channel 2 tracking/soft-start input | Sub-0.6V voltage forces output tracking; internal 1.4µA pull-up enables soft-start with external capacitor |
| ITH2 (Pin 11) | Channel 2 error amplifier output | Compensation node; connect RC network for loop stability; tie to INTVCC for internal compensation |
| VON2 (Pin 12) | Channel 2 on-time voltage input | Sets comparator threshold; tie to VOUT2 for VOUT-proportional on-time (0.6V–6V range) |
| SW2 (Pins 13,14) | Channel 2 switch node | Connects to external inductor; swings from ~–0.3V to VIN2; requires low-inductance layout |
| VIN2 (Pins 15,16) | Channel 2 power input | Independent supply input; supports different voltage than VIN1 (e.g., separate battery or rail) |
| BOOST2 (Pin 17) | Channel 2 bootstrap supply | Connects to (+) of bootstrap capacitor; swing range ≈ INTVCC–0.3V to VIN2+INTVCC |
| V2P5 (Pin 18) | 2.5V auxiliary regulator output | 10mA capable; bypass with ≥1µF ceramic; tie to INTVCC if unused to disable |
| INTVCC (Pin 19) | Internal 3.3V supply output | Powers internal logic/drivers; disabled when both RUN pins are low; decouple with ≥1µF ceramic |
| BOOST1 (Pin 20) | Channel 1 bootstrap supply | Functionally identical to BOOST2 but for first channel; shares same INTVCC source |
| VIN1 (Pins 21,22) | Channel 1 power input | Primary input for internal LDO generating INTVCC; supports same 3.6V–20V range as VIN2 |
| SW1 (Pins 23,24) | Channel 1 switch node | Functionally identical to SW2; layout symmetry critical for interleaved noise reduction |
| VON1 (Pin 25) | Channel 1 on-time voltage input | Same function and range as VON2; enables independent on-time scaling per channel |
| ITH1 (Pin 26) | Channel 1 error amplifier output | Same function as ITH2; allows independent loop compensation for each channel |
| TRACKSS1 (Pin 27) | Channel 1 tracking/soft-start input | Same function as TRACKSS2; enables independent soft-start timing per rail |
| VFB1 (Pin 28) | Channel 1 feedback input | Regulates VOUT1 using same 0.6V reference and error amplifier architecture as VFB2 |
| PGND (Exposed Pad) | Power ground return | Mandatory solder connection to PCB ground plane for thermal dissipation and low-impedance current return path |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3A synchronous buck channels | Monolithic integration eliminates external drivers/MOSFETs, reducing BOM count and board area |
| 180° interleaved phase operation | Halves effective input ripple frequency, cutting required input capacitance by ~30% versus in-phase |
| Burst Mode® and forced continuous modes | Enables <500µA quiescent current at light loads while maintaining fast transient response in continuous mode |
| Programmable 500kHz–4MHz switching frequency | Supports 1µH–2.2µH inductors and 22µF–47µF ceramic output caps across full operating range |
| Independent tracking and soft-start | Per-channel TRACKSS pins allow precise power sequencing for FPGAs, ASICs, and multi-rail processors |
| Integrated 2.5V and 3.3V auxiliary supplies | V2P5 and INTVCC outputs power external bias circuitry or level-shifters, reducing need for discrete regulators |
Applications
| Industrial PLC I/O Modules | FPGA Core & Auxiliary Power |
|---|---|
Use Scenario: Powering isolated analog front-ends and digital I/O banks in programmable logic controller modules requiring tight voltage tolerance and low noise. IC Role / Device Role / Timing Role: Dual-channel POL regulator supplying 3.3V I/O and 1.2V core rails with independent soft-start and PGOOD monitoring. Use Value: Interleaved 180° phase reduces conducted EMI on shared 24V DC input bus, easing EMC compliance in dense industrial enclosures. |
Use Scenario: Delivering tightly regulated core (0.85V–1.2V) and auxiliary (2.5V/3.3V) voltages to Xilinx or Intel FPGAs during configuration and runtime. IC Role / Device Role / Timing Role: Primary power controller managing rail sequencing, voltage margining, and dynamic load response for FPGA power domains. Use Value: Independent TRACKSS inputs enable precise power-up order matching FPGA vendor requirements, preventing latch-up or configuration failure. |
| Battery-Powered Test Equipment | Distributed Telecom Power Systems |
Use Scenario: Portable oscilloscopes and multimeters needing ultra-low standby current and rapid wake-up from sleep mode. IC Role / Device Role / Timing Role: Main system regulator converting 3S Li-ion (9–12.6V) to 3.3V logic and 5V analog rails with Burst Mode® operation. Use Value: Sub-500µA quiescent current extends battery life during idle periods without sacrificing transient response when active. |
Use Scenario: Remote radio units (RRUs) and small-cell base stations requiring redundant, high-efficiency 12V-to-3.3V/5V conversion with thermal resilience. IC Role / Device Role / Timing Role: Dual-output POL converter feeding RF transceivers and baseband processors from centralized 48V or 24V intermediate bus. Use Value: QFN-28 package with exposed PGND pad achieves 43°C/W θJA, enabling 3A/channel operation at 70°C ambient without forced air cooling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP8859GQ-Z (Monolithic Power) | Single-channel 6A output; no phase interleaving; fixed 500kHz/1MHz/2MHz options; no TRACKSS or V2P5 | Requires two devices for dual-rail; lacks independent soft-start and auxiliary supplies | Choose when higher per-channel current (>3A) is needed and dual-rail sequencing is handled externally |
| TPS544B25RTER (Texas Instruments) | Single-channel 4A; supports PMBus; 400kHz–2.2MHz sync range; no Burst Mode®; integrated EEPROM | No native dual-channel integration; requires external sequencing IC for multi-rail systems | Prefer when digital telemetry, margining, or firmware-configurable parameters are required over analog simplicity |
Compared with MP8859GQ-Z and TPS544B25RTER, the LTC3633AEUFD#PBF uniquely integrates dual 3A channels with per-rail tracking, soft-start, and auxiliary supplies in one QFN package-reducing component count and simplifying layout for space-constrained dual-rail designs where analog control and low IQ are prioritized over digital configurability.
Availability
LTC3633AEUFD#PBF is available at Aetrix Electronics and suitable for industrial PLC I/O modules, FPGA power delivery, battery-powered test equipment, and distributed telecom power systems requiring stable component supply and long-term production continuity.
Supply support for LTC3633AEUFD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for the LTC portfolio.
The LTC3633A series was designed specifically for high-density, high-efficiency dual-output point-of-load applications in battery-powered, industrial, and telecom infrastructure where thermal performance, sequencing control, and low-light-load IQ are critical.
FAQ
What is the absolute maximum input voltage rating for LTC3633AEUFD#PBF?
The LTC3633AEUFD#PBF has an absolute maximum VIN rating of 20V per channel, with overvoltage lockout triggering at 22.5V (rising) and releasing at 21.5V (falling). This 20V rating distinguishes it from the original LTC3633 (16V max) and confirms pin compatibility within the LTC3633A family.
Does LTC3633AEUFD#PBF support output voltage tracking between its two channels?
Yes, the LTC3633AEUFD#PBF supports independent output voltage tracking via dedicated TRACKSS1 and TRACKSS2 pins. Applying a ramp voltage below 0.6V to either pin forces the corresponding channel's output to follow that ramp, enabling precise power sequencing for multi-rail ICs like FPGAs and DSPs.
Can LTC3633AEUFD#PBF operate with only one channel enabled?
Yes, LTC3633AEUFD#PBF supports independent channel enable/disable via RUN1 and RUN2 pins. Either channel can be disabled while the other remains fully operational, with no impact on the enabled channel's regulation, efficiency, or protection features.
What is the minimum on-time specification for LTC3633AEUFD#PBF and why does it matter?
The LTC3633AEUFD#PBF has a minimum on-time of 20ns (at VON = 0.6V, VIN = 4V), enabling stable operation at high step-down ratios (e.g., 12V-to-1.2V at 1MHz) without pulse-skipping or frequency foldback. This ensures consistent transient response and low output ripple across wide VIN/VOUT combinations.
How does the PHMODE pin affect input capacitor requirements in LTC3633AEUFD#PBF designs?
When PHMODE is set high for 180° out-of-phase operation, the LTC3633AEUFD#PBF interleaves channel switching, reducing RMS input current by up to 30% compared to in-phase operation. This directly lowers required input capacitance and eases thermal stress on bulk capacitors in high-current applications.
LTC3633AEUFD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 3.6V
- Voltage - Input (Max):
- 20V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 6V
- Current - Output:
- 3A
- Frequency - Switching:
- 500kHz ~ 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-QFN (4x5)
LTC3633AEUFD#PBF FAQ
1.How can I place an order for LTC3633AEUFD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3633AEUFD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3633AEUFD#PBF reliable?
The price and inventory of LTC3633AEUFD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3633AEUFD#PBF is usually 5 days.
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5.How can I obtain technical support or documentation for LTC3633AEUFD#PBF?
For technical support, including LTC3633AEUFD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3633AEUFD#PBF requirements.
6.How does Aetrix verify that LTC3633AEUFD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3633AEUFD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3633AEUFD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3633AEUFD#PBF?
All LTC3633AEUFD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3633AEUFD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3633AEUFD#PBF part is unused and in its original packaging.
Return procedure for LTC3633AEUFD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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