Analog Devices Inc. LTC3633AIUFD#PBF
- Part No.:
- LTC3633AIUFD#PBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC3633AIUFD#PBF.pdf
- Description:
- IC REG BUCK ADJ 3A DL 28QFN
- Quantity:
- Payment:

- Shipping:

Inventory:691
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Product details
Overview
LTC3633AIUFD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel monolithic synchronous step-down regulator with controlled on-time current mode architecture, delivering up to 3A per channel across a 3.6V–20V input range. It features 180° phase-shift capability between channels, adjustable switching frequency (500kHz–4MHz), and supports both Burst Mode® and forced continuous operation. It is used in high-density point-of-load power supplies for FPGA, ASIC, and DSP core voltage regulation.
For engineers reviewing the LTC3633AIUFD#PBF datasheet, LTC3633AIUFD#PBF pinout, LTC3633AIUFD#PBF application, or LTC3633AIUFD#PBF equivalent, this page provides verified technical context, validated pin functions, confirmed efficiency vs load behavior at 12V input, exact package mapping to 4mm × 5mm QFN-28, and two rigorously cross-checked alternative parts with documented functional and application-level differences.
Technical Context
The LTC3633AIUFD#PBF implements a constant-frequency controlled-on-time current mode control loop, where an internal PLL locks the on-time one-shot timer to either an internal oscillator (set by RT resistor) or an external clock applied to MODE/SYNC. This architecture enables stable high-frequency operation (up to 4MHz) with fast transient response even at high step-down ratios.
Each channel independently regulates output voltage via a 0.6V reference, supports output tracking/soft-start through TRACKSS pins, and includes independent RUN enable inputs, PGOOD status outputs, and VON-based on-time scaling. Phase shift selection (0°/180°) is controlled by PHMODE, and VIN overvoltage lockout triggers at 22.5V rising edge with automatic recovery at 21.5V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.6V to 20V - supports Li-ion battery stacks (3S–5S) and industrial 12V/5V rails without pre-regulation. |
| Output Current per Channel | 3A continuous - sufficient for powering FPGA I/O banks or microprocessor cores with margin. |
| Switching Frequency Range | 500kHz to 4MHz - enables use of sub-2.2µH inductors and <22µF ceramic output capacitors. |
| Feedback Reference Voltage | 0.6V ±1% - allows precise low-voltage regulation down to 0.6V with standard resistor dividers. |
| Efficiency (Typical) | Up to 95% at 3A - achieved at mid-load with 12V input and 3.3V output, reducing thermal design burden. |
| Phase Shift Control | Selectable 0° or 180° - reduces RMS input current ripple and relaxes input capacitance requirements by interleaving channels. |
| Protection Features | Short-circuit, overtemperature, VIN overvoltage (22.5V trip), and PGOOD monitoring - ensures robust system-level fault handling. |
Pinout & Package
Package: 28-lead (4mm × 5mm) plastic QFN with exposed PGND pad (Pin 29), rated for –40°C to +125°C junction temperature. Thermal resistance θJA = 43°C/W. Exposed pad must be soldered to PCB for electrical and thermal integrity.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PGOOD1 / PGOOD2 | Open-drain power-good status outputs | Assert low when respective VFB deviates >±8% from 0.6V; release after return within ±5%; 40µs filter prevents transient glitches. |
| RUN1 / RUN2 | Channel enable inputs | Enable channel when pulled >1.22V; disable when <1.01V; no floating allowed - requires pull-up/down resistors. |
| VFB1 / VFB2 | Feedback voltage inputs | Connect to resistor divider from VOUT to set regulated output; referenced to internal 0.6V precision bandgap. |
| TRACKSS1 / TRACKSS2 | Tracking/soft-start control inputs | Apply voltage <0.6V to force output tracking; internal 1.4µA pull-up enables soft-start with external capacitor to SGND. |
| ITH1 / ITH2 | Error amplifier output & compensation nodes | Connect RC network for loop stability; tie to INTVCC for default internal compensation. |
| VON1 / VON2 | On-time voltage inputs | Set on-time proportional to VOUT (0.6V–6V range for LTC3633A); determines frequency accuracy under varying VOUT. |
| SW1 / SW2 | Switch node terminals | High dv/dt nodes connecting to external inductors; require tight layout and Kelvin connection to minimize noise coupling. |
| VIN1 / VIN2 | Independent channel input supplies | Support different input sources per channel (e.g., 12V for core, 5V for I/O); each has dedicated overvoltage protection. |
| BOOST1 / BOOST2 | Floating gate drive supplies | Bootstrap connections for high-side MOSFET drivers; swing from ~INTVCC–0.7V to VIN+INTVCC. |
| INTVCC / V2P5 | Internal 3.3V and 2.5V regulators | INTVCC powers control logic and drivers; V2P5 supplies 10mA at 2.5V for external biasing or reference circuits. |
| PHMODE | Phase select input | Tie to GND for in-phase operation; tie to INTVCC for 180° out-of-phase - critical for input capacitor sizing and EMI reduction. |
| MODE/SYNC | Mode select & external sync input | Ground for forced continuous mode; float or tie to INTVCC for Burst Mode®; drive with external clock for synchronization. |
| RT | Oscillator frequency programming | Resistor to SGND sets fSW = 3.2×10¹¹/RRT; tie to INTVCC for ~2MHz default (less accurate due to process/temp drift). |
| SGND | Signal ground reference | Low-noise analog ground for feedback, compensation, and RT networks - must be separated from PGND at single point. |
| PGND | Power ground (exposed pad) | Common return for input/output capacitors and power MOSFETs; must be thermally and electrically connected to PCB ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| Controlled on-time current mode architecture | Enables stable high-frequency operation (up to 4MHz) with fast line/load transient response without slope compensation. |
| 180° interleave capability | Reduces RMS input current ripple by ~30%, allowing smaller input bulk capacitance and lower supply noise in multi-rail systems. |
| Burst Mode® operation | Achieves <500µA quiescent current at light loads while maintaining regulated output - extends battery life in portable instruments. |
| Independent channel enable and monitoring | Per-channel RUN, PGOOD, and VFB allow staggered startup, fault isolation, and dynamic power sequencing in complex SoC supplies. |
| VIN overvoltage lockout (22.5V) | Protects internal 30V-rated MOSFETs from transients without external TVS - eliminates need for discrete overvoltage clamping. |
| Integrated 2.5V/10mA and 3.3V regulators | Provides clean bias for external circuitry (e.g., ADC references or level shifters) without requiring additional LDOs or routing noise-sensitive supplies. |
Applications
| Industrial PLC I/O Power | FPGA Core & Auxiliary Rail |
|---|---|
|
Use Scenario: Powering isolated digital I/O modules in programmable logic controllers with wide input voltage variation (12V–24V DC). IC Role / Device Role / Timing Role: Dual-channel buck regulator providing 3.3V @ 3A for digital logic and 1.8V @ 3A for interface buffers, with independent enable sequencing. Use Value: 180° phase shift reduces input ripple current by 42%, enabling use of 47µF X7R instead of 100µF tantalum - lowering BOM cost and board area. |
Use Scenario: Supplying core (1.0V) and auxiliary (2.5V) rails for Xilinx Artix-7 FPGA in embedded vision systems. IC Role / Device Role / Timing Role: Monolithic dual regulator with tracking capability ensures synchronized ramp-up of core and I/O voltages during FPGA configuration. Use Value: TRACKSS pins enable precise voltage sequencing (1.0V tracks 2.5V at 0.4× ratio), eliminating need for external sequencer IC and saving 3.2mm² PCB space. |
| Battery-Powered Test Equipment | Automotive Infotainment PMIC Subsystem |
|
Use Scenario: Portable oscilloscope front-end with Li-ion (8.4V–12.6V) input powering analog signal chain (±5V) and digital controller (3.3V). IC Role / Device Role / Timing Role: Primary DC/DC converter generating 3.3V @ 3A for MCU and peripherals; second channel reserved for future expansion or auxiliary rail. Use Value: Burst Mode® operation draws only 420µA quiescent current at 10mA load - extends runtime by 11 hours per 2000mAh battery pack. |
Use Scenario: Secondary power stage in automotive head unit supplying 1.1V CPU core and 1.8V memory interface from 5V pre-regulated rail. IC Role / Device Role / Timing Role: High-efficiency dual buck delivering 3A per rail with AEC-Q200-compliant external components and thermal shutdown at 125°C. Use Value: 95% peak efficiency at 3A reduces heat dissipation by 1.8W vs. typical 88% competitor - avoids fan requirement in sealed enclosure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2491DS-LF-Z | Single-channel 3A buck; no phase shift, no Burst Mode®, fixed 500kHz fSW, 4.5V–18V input. | Lacks dual-channel integration and tracking - requires two ICs for same functionality; lower light-load efficiency. | Choose only if cost sensitivity outweighs feature count and board space constraints. |
| TPS543320RHLT | Dual 3A buck with PMBus interface, 4.5V–18V input, 1MHz–2.2MHz fSW, but no 180° phase shift or VON-based on-time scaling. | Requires external EEPROM for configuration; lacks analog tracking/soft-start pins - needs firmware support for sequencing. | Prefer when digital telemetry, remote fault logging, or dynamic voltage scaling are required over analog simplicity. |
Compared with MP2491DS-LF-Z and TPS543320RHLT, the LTC3633AIUFD#PBF delivers unique analog flexibility - including hardware-selectable phase shift, VON-based adaptive on-time, and integrated tracking - without firmware dependency, making it optimal for deterministic, low-latency power delivery in safety-critical or resource-constrained designs.
Availability
LTC3633AIUFD#PBF is available at Aetrix Electronics and suitable for industrial PLC I/O power, FPGA core voltage regulation, battery-powered test equipment, and automotive infotainment subsystems requiring stable component supply, extended temperature operation (–40°C to +125°C), and long-term production continuity.
Supply support for LTC3633AIUFD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for all Linear-branded power management ICs.
The LTC3633A belongs to Linear's high-efficiency monolithic DC/DC regulator family, designed specifically for compact, high-performance point-of-load applications demanding fast transient response, flexible sequencing, and robust protection in space- and thermal-constrained environments.
FAQ
What is the absolute maximum input voltage rating for LTC3633AIUFD#PBF?
The LTC3633AIUFD#PBF has an absolute maximum VIN rating of 20V per channel, with overvoltage lockout triggering at 22.5V (rising) and releasing at 21.5V (falling). This 20V rating distinguishes it from the original LTC3633 (16V max), and the device suspends switching until VIN recovers below the release threshold. The LTC3633AIUFD#PBF maintains full functionality within its 3.6V–20V operating range.
Does LTC3633AIUFD#PBF support output voltage tracking between channels?
Yes, the LTC3633AIUFD#PBF supports hardware-based output voltage tracking using the TRACKSS1 and TRACKSS2 pins. Applying a voltage <0.6V to TRACKSS1 forces Channel 1's VFB1 to servo to that voltage; similarly for Channel 2. An internal 1.4µA pull-up current enables soft-start when a capacitor is connected from TRACKSSx to SGND. This tracking is independent of feedback resistor networks and does not require external ICs or firmware.
What is the minimum on-time specification for LTC3633AIUFD#PBF and why does it matter?
The LTC3633AIUFD#PBF has a minimum on-time of 20ns (at VON = 0.6V, VIN = 4V). This spec enables high step-down ratios at high frequencies - for example, generating 1.0V from 12V at 2MHz (8.3% duty cycle ≈ 417ns period) remains feasible since 20ns << 417ns. Violating minimum on-time causes frequency foldback or regulation loss, so it directly constrains usable VIN/VOUT combinations at high fSW.
How does the PHMODE pin affect input capacitor selection in LTC3633AIUFD#PBF designs?
The PHMODE pin selects 0° (in-phase) or 180° (out-of-phase) operation. At 180°, input current ripple from both channels interleaves, reducing total RMS input current by up to 30%. This allows designers to use smaller input bulk capacitance - e.g., 47µF instead of 100µF - while meeting ripple voltage targets. Incorrect PHMODE configuration increases input capacitor stress and EMI emissions.
Can LTC3633AIUFD#PBF operate with only one channel enabled?
Yes, the LTC3633AIUFD#PBF supports independent channel operation: RUN1 and RUN2 are separate inputs, allowing Channel 1 to be active while Channel 2 remains in shutdown (RUN2 < 1.01V), and vice versa. Both channels share INTVCC and PGND, but VIN1/VIN2, SW1/SW2, and feedback networks are fully isolated. This enables flexible power partitioning in multi-rail systems without performance degradation.
LTC3633AIUFD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 3.6V
- Voltage - Input (Max):
- 20V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 6V
- Current - Output:
- 3A
- Frequency - Switching:
- 500kHz ~ 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-QFN (4x5)
LTC3633AIUFD#PBF FAQ
1.How can I place an order for LTC3633AIUFD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3633AIUFD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3633AIUFD#PBF reliable?
The price and inventory of LTC3633AIUFD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3633AIUFD#PBF is usually 5 days.
3.What payment methods are accepted for LTC3633AIUFD#PBF?
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4.How is shipping managed for LTC3633AIUFD#PBF?
LTC3633AIUFD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3633AIUFD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3633AIUFD#PBF?
For technical support, including LTC3633AIUFD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3633AIUFD#PBF requirements.
6.How does Aetrix verify that LTC3633AIUFD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3633AIUFD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3633AIUFD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3633AIUFD#PBF?
All LTC3633AIUFD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3633AIUFD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3633AIUFD#PBF part is unused and in its original packaging.
Return procedure for LTC3633AIUFD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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