My Inquiry
My Account
Analog Devices Inc. LTC3633IUFD#TRPBF
- Part No.:
- LTC3633IUFD#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC3633IUFD#TRPBF.pdf
- Description:
- IC REG BUCK ADJ 3A DL 28QFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,686
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3633IUFD#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel monolithic synchronous step-down regulator delivering 3A per channel from 3.6V–15V input, featuring controlled-on-time current-mode architecture, 180° phase-shifted operation, and programmable 500kHz–4MHz switching frequency. It serves as a high-efficiency point-of-load power supply for FPGA core/logic rails, DSP I/O domains, and battery-powered instrumentation requiring tight regulation and fast transient response.
For engineers reviewing the LTC3633IUFD#TRPBF datasheet, LTC3633IUFD#TRPBF pinout, LTC3633IUFD#TRPBF application, or LTC3633IUFD#TRPBF equivalent, key selection criteria include dual 3A output capability with interleaved phase control, ±5% PGOOD accuracy, 0.6V reference for low-VOUT designs, and QFN-28 thermal performance at –40°C to 125°C junction temperature.
Technical Context
The LTC3633IUFD#TRPBF implements a constant-frequency, current-mode control loop with internal error amplifier (1.8mS transconductance), valley-current sensing via SW–PGND voltage drop, and phase-locked on-time servoing to maintain precise switching frequency across line/load/temperature. Its dual-channel architecture supports independent enable (RUN1/RUN2), feedback (VFB1/VFB2), and soft-start/tracking (TRACKSS1/TRACKSS2) for coordinated power sequencing.
It integrates two matched 130mΩ top / 65mΩ bottom N-channel MOSFETs per channel, a 3.3V INTVCC LDO powered from VIN1, a 2.5V V2P5 auxiliary regulator (10mA), and comprehensive protection including VIN overvoltage lockout (16.5V–17.5V), overtemperature shutdown, and short-circuit current limiting (2.6A–4.5A positive valley limit).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.6V to 15V - supports dual-cell Li-ion (7.2V–8.4V), 12V industrial rails, and 5V backplane inputs without external pre-regulation. |
| Output Current per Channel | 3A continuous - enables single-chip dual-rail power for FPGA core + I/O or processor + memory subsystems. |
| Switching Frequency | 500kHz to 4MHz - adjustable via RT resistor; allows optimization between small magnetics (high-f) and peak efficiency (low-f). |
| Reference Voltage | 0.6V ±1% - enables precise low-output voltages (e.g., 0.9V, 1.2V) using standard resistor dividers with minimal error contribution. |
| Efficiency | Up to 95% - achieved at full load with optimized inductor/capacitor selection; Burst Mode extends light-load efficiency. |
| Thermal Performance | θJA = 43°C/W (QFN-28) - requires exposed PGND pad soldering; supports 3A/channel operation up to 125°C junction temperature. |
| Protection Features | VIN overvoltage lockout (16.5V trip), overtemperature shutdown, short-circuit current limit, and PGOOD with 40µs glitch filter. |
Pinout & Package
Package: 28-lead (4mm × 5mm) plastic QFN with exposed PGND pad (Pin 29), rated for –40°C to 125°C operating junction temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PGOOD1 / PGOOD2 | Open-drain power-good status outputs | Assert low when respective VFB deviates >±8% from 0.6V; release after return to ±5% window with 40µs filter - enables reliable system power sequencing. |
| RUN1 / RUN2 | Channel enable inputs | Active-high logic: >1.22V enables regulation; <1.01V forces shutdown - supports independent channel control and sequencing. |
| PHMODE | Phase select input | Tied to GND → in-phase switching; tied to INTVCC → 180° out-of-phase - reduces RMS input current and relaxes input capacitance requirements. |
| MODE/SYNC | Mode select & sync input | GND → forced continuous mode; floating/INTVCC → Burst Mode; driven clock → synchronization with PLL lock - enables flexible efficiency vs noise trade-offs. |
| RT | Oscillator frequency program | Resistor-to-SGND sets fSW = 3.2×10¹¹/RRT Hz (500kHz–4MHz); tied to INTVCC → ~2MHz default - enables precise frequency control without external clock source. |
| VFB1 / VFB2 | Feedback inputs | Connect to resistor divider from VOUT to set output voltage per VOUT = 0.6V × (1 + R1/R2) - provides stable regulation with 0.05% load regulation. |
| TRACKSS1 / TRACKSS2 | Tracking/soft-start inputs | Apply voltage <0.6V to track external rail; capacitor-to-SGND enables linear soft-start via 1.4µA internal pull-up - ensures monotonic startup and voltage coordination. |
| ITH1 / ITH2 | Error amplifier outputs | Loop compensation nodes: connect RC network for stability; tie to INTVCC for internal compensation - simplifies design for standard applications. |
| VON1 / VON2 | On-time voltage inputs | Set on-time proportional to VOUT when tied to output (valid for VOUT <6V) - maintains constant frequency during variable-output operation. |
| SW1 / SW2 | Switch node connections | High-side/Low-side MOSFET drains - require low-inductance layout to PGND and proper bootstrap capacitor placement on BOOSTx pins. |
| VIN1 / VIN2 | Independent input supplies | Accept separate 3.6V–15V sources per channel - enables split-rail inputs or redundancy; VIN1 powers INTVCC LDO. |
| BOOST1 / BOOST2 | Floating gate drive supplies | Bootstrap capacitor (+) terminals - swing from ~2.6V below INTVCC to VIN+INTVCC; critical for high-side NMOS gate drive integrity. |
| INTVCC | Internal 3.3V regulator output | Powers control circuitry and drivers; disabled when both RUN pins are low - decouple with ≥1µF ceramic capacitor to PGND. |
| V2P5 | Auxiliary 2.5V regulator output | Supplies 10mA; bypass with ≥1µF ceramic; tie to INTVCC if unused - provides clean bias for external references or level-shifting circuits. |
| SGND | Signal ground reference | Low-noise analog ground for feedback dividers, RT, and compensation networks - must be isolated from PGND except at single-point connection. |
| PGND | Power ground (exposed pad) | Return path for input/output capacitors and MOSFET sources - must be soldered to PCB thermal pad for electrical continuity and thermal dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 3A synchronous buck channels | Integrated 130mΩ/65mΩ MOSFETs per channel eliminate external power switches and reduce BOM count and layout area. |
| 180° interleaved phase operation | Halves RMS input current ripple versus in-phase operation, reducing required input capacitance by ~50% and lowering supply noise. |
| Burst Mode® vs forced continuous selection | User-selectable via MODE/SYNC pin - achieves <500µA quiescent current in Burst Mode while maintaining fast transient response in forced mode. |
| 0.6V precision reference with tracking | Enables accurate low-VOUT regulation (e.g., 0.9V, 1.05V) and seamless power-rail sequencing across multiple ICs using TRACKSS pins. |
| Comprehensive fault protection | Includes VIN overvoltage lockout (16.5V/17.5V hysteresis), overtemperature shutdown, and cycle-by-cycle current limiting with negative valley detection. |
| Programmable soft-start and power-good | Adjustable startup time via TRACKSS capacitor; PGOOD with ±5% release threshold and 40µs filtering prevents false resets during transients. |
Applications
| FPGA Core & I/O Power | DSP/Processor Dual-Rail Supply |
|---|---|
|
Use Scenario: Powering Xilinx Artix-7 FPGA core (0.95V/2.5A) and bank I/O (1.8V/2.2A) from a 12V intermediate bus. IC Role / Device Role / Timing Role: Dual-channel synchronous buck regulator providing independently regulated, sequenced, and monitored power rails. Use Value: Eliminates need for two discrete regulators; 180° phase shift cuts input capacitor count by 30%; PGOOD signals enable safe configuration loading. |
Use Scenario: Supplying TI C66x DSP core (1.0V/2.8A) and memory interface (1.5V/2.1A) in radar signal processing module. IC Role / Device Role / Timing Role: High-efficiency, thermally robust point-of-load regulator with soft-start coordination and rail tracking. Use Value: Achieves >92% efficiency at full load; TRACKSS pins ensure core powers before I/O; QFN-28 package fits dense RF board layouts. |
| Battery-Powered Test Instrumentation | Industrial PLC I/O Module |
|
Use Scenario: Generating 3.3V/3A and 5V/3A from dual-cell Li-ion (7.2V–8.4V) in portable oscilloscope front-end. IC Role / Device Role / Timing Role: Input-voltage-flexible dual buck converter with Burst Mode for extended battery life and forced mode for measurement stability. Use Value: Delivers >88% efficiency at 10mA (Burst Mode) and >94% at 2A; wide VIN range avoids buck-boost complexity; V2P5 powers ADC reference. |
Use Scenario: Providing isolated 24V-to-3.3V/3A and 5V/3A rails for microcontroller and fieldbus transceivers in DIN-rail mounted PLC. IC Role / Device Role / Timing Role: Robust, temperature-rated DC-DC regulator handling 125°C ambient with overvoltage/overtemperature protection. Use Value: Guaranteed operation from –40°C to 125°C; VIN OVLO protects against 24V supply surges; PGND pad ensures thermal reliability in sealed enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS54383RTER | 3A dual-channel buck; fixed 3.5MHz frequency; no phase-shift control; lower max VIN (18V); integrated compensation. | Lacks 180° interleaving and VIN OVLO; better suited for space-constrained, fixed-frequency apps where input ripple is less critical. | Select when board area is priority and input capacitance can be oversized; avoid where input bus noise or surge immunity is required. |
| MP2491DS-LF-Z | 3A dual buck; 500kHz–2.5MHz sync-capable; no Burst Mode; 0.8V ref; smaller 3mm×4mm QFN-22 package. | Higher quiescent current (>1mA); no auxiliary 2.5V rail; limited thermal margin at 125°C ambient due to smaller package. | Choose for cost-sensitive, lower-temperature environments; not recommended for extended 125°C operation or low-IQ battery systems. |
Compared with TPS54383RTER and MP2491DS-LF-Z, the LTC3633IUFD#TRPBF uniquely combines 180° phase interleaving, programmable Burst Mode, VIN overvoltage lockout, and a dedicated 2.5V auxiliary rail - making it optimal for thermally demanding, noise-sensitive, or battery-operated dual-rail systems requiring high reliability and design flexibility.
Availability
LTC3633IUFD#TRPBF is available at Aetrix Electronics and suitable for FPGA power delivery, industrial PLC modules, and battery-powered test equipment requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC3633IUFD#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance power management portfolio with rigorous automotive and industrial qualification standards.
The LTC3633 belongs to Linear's monolithic synchronous buck regulator family, designed specifically for high-density, high-efficiency point-of-load conversion in FPGA, ASIC, and DSP applications where thermal performance, sequencing, and reliability are critical.
FAQ
What is the guaranteed operating temperature range for the LTC3633IUFD#TRPBF?
The LTC3633IUFD#TRPBF is specified and tested over a –40°C to 125°C junction temperature range. This "I" grade rating ensures full electrical performance compliance across industrial and extended-temperature environments, unlike the "E" grade (0°C to 85°C). Thermal design must maintain TJ ≤ 125°C using the QFN-28 package's θJA = 43°C/W and proper PGND pad soldering.
How does the PHMODE pin affect input capacitor requirements in the LTC3633IUFD#TRPBF?
The PHMODE pin configures the LTC3633IUFD#TRPBF for either in-phase or 180° out-of-phase switching. When set to 180° (PHMODE = INTVCC), input current pulses from each channel are interleaved, reducing RMS input ripple by up to 30%. This directly lowers the required input capacitance value and ESR, enabling fewer or smaller ceramic capacitors on the VIN bus compared to in-phase operation.
Can the LTC3633IUFD#TRPBF regulate two different output voltages simultaneously?
Yes, the LTC3633IUFD#TRPBF supports independent output voltages via separate feedback networks on VFB1 and VFB2. Each channel uses the same 0.6V internal reference, so VOUT1 = 0.6V × (1 + R1/R2) and VOUT2 = 0.6V × (1 + R3/R4). The device also supports tracking (via TRACKSS1/TRACKSS2) for coordinated startup, but steady-state regulation remains fully independent per channel.
What protection features are built into the LTC3633IUFD#TRPBF?
The LTC3633IUFD#TRPBF integrates VIN overvoltage lockout (trip at 17.5V, release at 16.5V), overtemperature shutdown, cycle-by-cycle valley current limiting (2.6A–4.5A), short-circuit protection, and PGOOD monitoring with ±5% release hysteresis and 40µs glitch filtering. These features operate autonomously without external components, ensuring robust operation under fault conditions.
Is the V2P5 output on the LTC3633IUFD#TRPBF mandatory to use?
No, the V2P5 output is optional. It delivers a regulated 2.5V at up to 10mA and must be bypassed with ≥1µF ceramic if used. If unused, V2P5 should be tied directly to INTVCC to disable the LDO and prevent floating node issues. Leaving V2P5 unconnected is not permitted, as it may cause instability or increased quiescent current.
LTC3633IUFD#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Adjustable
- Number of Outputs:
- 2
- Voltage - Input (Min):
- 3.6V
- Voltage - Input (Max):
- 15V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 14.7V
- Current - Output:
- 3A
- Frequency - Switching:
- 500kHz ~ 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-QFN (4x5)
LTC3633IUFD#TRPBF FAQ
1.How can I place an order for LTC3633IUFD#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3633IUFD#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3633IUFD#TRPBF reliable?
The price and inventory of LTC3633IUFD#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3633IUFD#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC3633IUFD#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3633IUFD#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3633IUFD#TRPBF?
LTC3633IUFD#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3633IUFD#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3633IUFD#TRPBF?
For technical support, including LTC3633IUFD#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3633IUFD#TRPBF requirements.
6.How does Aetrix verify that LTC3633IUFD#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC3633IUFD#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3633IUFD#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC3633IUFD#TRPBF?
All LTC3633IUFD#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3633IUFD#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3633IUFD#TRPBF part is unused and in its original packaging.
Return procedure for LTC3633IUFD#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3633IUFD#TRPBF Tags
-
TPS562201DDCR
Texas Instruments
-
MC34063ABD-TR
STMicroelectronics
-
TPS561201DDCR
Texas Instruments
-
MC33063ADR
Texas Instruments
-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments
-
AP3012KTR-G1
Diodes Incorporated
-
TLV61048DBVR
Texas Instruments
-
AZ34063UMTR-G1
Diodes Incorporated
-
TPS562200DDCR
Texas Instruments
-
AP62300TWU-7
Diodes Incorporated
-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
