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Analog Devices Inc. LTC3634EFE#PBF
- Part No.:
- LTC3634EFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC3634EFE#PBF.pdf
- Description:
- IC REG CONV DDR 2OUT 28TSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:2,597
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Product details
Overview
LTC3634EFE#PBF from Analog Devices (formerly Linear Technology) is a dual-channel monolithic synchronous step-down regulator optimized for DDR1/DDR2/DDR3 memory power supplies, delivering ±3A per channel with 0.6V–3V output range, 500kHz–4MHz programmable switching frequency, and 180° out-of-phase operation to reduce input RMS current. It integrates VTT termination and VTTR reference generation for bus compliance in high-speed memory subsystems.
For engineers reviewing the LTC3634EFE#PBF datasheet, LTC3634EFE#PBF pinout, LTC3634EFE#PBF application, or LTC3634EFE#PBF equivalent, key selection criteria include its dual-channel current-mode control, ±1.6% VTTR accuracy at 0.75V, 3.6V–15V input range, integrated 3.3V INTVCC LDO, and thermal-enhanced 28-lead TSSOP package with exposed PGND pad.
Technical Context
The LTC3634EFE#PBF employs a controlled on-time current-mode architecture enabling stable high-frequency operation (up to 4MHz) from 12V input while maintaining low duty-cycle regulation down to 0.6V. Its dual independent channels support asynchronous or synchronized 90°/180° phase-shifted operation via PHMODE pin control.
Channel 1 features Burst Mode® operation for light-load efficiency, while Channel 2 operates continuously and uses VTTR (VDDQIN/2) as its feedback reference-enabling precise DDR termination voltage tracking. Both channels integrate valley-current limiting (±3.3A to ±5.5A), input overvoltage lockout (16.5V–17.5V), and thermal shutdown protection.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.6V to 15V - supports direct connection to 5V/12V rails and battery-powered DDR systems |
| Output Current per Channel | ±3A - delivers full DDR3 VTT sink/source capability without external FETs |
| VTTR Accuracy | ±1.6% at 0.75V - ensures compliant DDR reference voltage for VDDQIN = 1.5V–2.6V |
| Switching Frequency Range | 500kHz to 4MHz - adjustable via RT resistor; enables compact magnetics and low output ripple |
| Phase Shift Options | 90° or 180° - reduces input capacitor RMS stress and improves EMI profile |
| Package Thermal Resistance | θJA = 25°C/W (TSSOP) - enables higher sustained power delivery vs QFN in constrained layouts |
| Operating Junction Temp | –40°C to +125°C - qualified for industrial-grade DDR power applications |
Pinout & Package
The LTC3634EFE#PBF is housed in a thermally enhanced 28-lead plastic TSSOP package with exposed PGND pad (Pin 29), requiring soldering to PCB for thermal and electrical integrity. θJA = 25°C/W enables higher continuous power dissipation than the QFN variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PGOOD1 (Pin 1) | Channel 1 Power Good Output | Open-drain signal pulled low if VFB1 deviates >±8% from 0.6V reference; includes 15mV hysteresis and 40µs glitch filter |
| PHMODE (Pin 2) | Phase Select Input | Ground = 90° phase shift; INTVCC = 180° phase shift - enables interleaved input current reduction |
| RUN1 (Pin 3) | Channel 1 Enable | Active-high enable: >1.22V starts regulation; <1.01V forces shutdown with <1µA quiescent current |
| MODE/SYNC (Pin 4) | Channel 1 Mode Control / Sync Input | Ground = forced continuous mode; floating/INTVCC = Burst Mode®; external clock = synchronization with PLL lock |
| RT (Pin 5) | Oscillator Frequency Set | Resistor to SGND programs fSW from 500kHz–4MHz; tied to INTVCC = 2MHz default |
| RUN2 (Pin 6) | Channel 2 Enable | Independent enable with same threshold as RUN1; controls VTT rail activation separately from VDDQ |
| SGND (Pin 7) | Signal Ground Reference | Low-noise analog ground for feedback dividers, compensation networks, and RT resistor |
| PGOOD2 (Pin 8) | Channel 2 Power Good Output | Open-drain signal pulled low if VFB2 deviates >±8% from VTTR; asserts low below 300mV VTTR |
| VFB2 (Pin 9) | Channel 2 Feedback Input | Connects directly to VTT output to regulate against VTTR reference; enables precise DDR termination |
| VDDQIN (Pin 10) | External Reference Input | Sets VTTR = VDDQIN × 0.5; supports 1.5V–2.6V range for DDR1/2/3 VDDQ supply tracking |
| ITH2 (Pin 11) | Channel 2 Error Amplifier Output | Compensation node for loop stability; connects to RC network to set crossover frequency and phase margin |
| VON2 (Pin 12) | Channel 2 On-Time Voltage Input | Tied to VTT output to make on-time proportional to VOUT2 (<3V); enables constant frequency across load |
| SW2 (Pins 13,14) | Channel 2 Switch Node | Connects to external inductor; voltage swings from ~–0.3V to VIN2 + 0.3V during operation |
| VIN2 (Pins 15,16) | Channel 2 Power Input | Independent 3.6V–15V input for VTT rail; may differ from VIN1 to support split-rail DDR designs |
| BOOST2 (Pin 17) | Channel 2 Bootstrap Supply | Floating gate drive supply for top MOSFET; capacitor connects between BOOST2 and SW2 |
| VTTR (Pin 18) | DDR Reference Output | Buffered VDDQIN/2 output; ±10mA drive capability; 0.01µF max capacitive load; used as VFB2 reference |
| INTVCC (Pin 19) | Internal 3.3V Regulator | Supplies gate drivers and logic; requires ≥1µF ceramic decoupling to PGND; disabled when both RUN pins are low |
| BOOST1 (Pin 20) | Channel 1 Bootstrap Supply | Floating gate drive supply for Channel 1 top MOSFET; capacitor connects between BOOST1 and SW1 |
| VIN1 (Pins 21,22) | Channel 1 Power Input | 3.6V–15V input for VDDQ rail; powers internal INTVCC LDO; may be shared or isolated from VIN2 |
| SW1 (Pins 23,24) | Channel 1 Switch Node | Connects to external inductor; voltage swings from ~–0.3V to VIN1 + 0.3V; drives high-side MOSFET gate |
| VON1 (Pin 25) | Channel 1 On-Time Voltage Input | Tied to VDDQ output to scale on-time with VOUT1 (<3V); maintains fixed frequency under load transients |
| ITH1 (Pin 26) | Channel 1 Error Amplifier Output | Compensation node for VDDQ loop; connects to RC network matching Channel 2 for balanced dynamics |
| TRACKSS (Pin 27) | Tracking/Soft-Start Input | Below 0.6V enables output tracking; internal 1.4µA pull-up enables soft-start with external capacitor to SGND |
| VFB1 (Pin 28) | Channel 1 Feedback Input | Connects to resistor divider from VDDQ to set output voltage; internal 0.6V reference enables 0.6V–3V range |
| PGND (Exposed Pad) | Power Ground | Common return for input/output capacitors and MOSFET sources; must be soldered to PCB for thermal and EMI performance |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent DDR power rails | Simultaneous VDDQ (0.6–3V, ±3A) and VTT (0.75V nominal, ±3A) with separate inputs, enables split-rail DDR3 designs |
| VTTR buffered reference output | ±10mA capable, ±1.6% accuracy at 0.75V, drives DDR VREF directly without external op-amp or divider |
| Controlled on-time current-mode control | Enables stable 12V-to-0.9V conversion at 2MHz with fast transient response and no right-half-plane zero compensation |
| 180° interleaved switching | Reduces input capacitor RMS current by up to 30%, lowers required CIN value and supply noise on shared 12V bus |
| Burst Mode® on Channel 1 | Improves light-load efficiency to >85% at 10mA VDDQ load while maintaining tight output regulation |
| Integrated protection suite | Includes input overvoltage lockout (16.5V–17.5V), thermal shutdown, short-circuit current limiting, and PGOOD status with filtering |
Applications
| DDR3 Memory Power Supply | DDR2 Termination System |
|---|---|
Use Scenario: Powering DDR3 SDRAM modules in industrial embedded controllers requiring stable 1.5V VDDQ and 0.75V VTT with ±3A sink/source capability. IC Role / Device Role / Timing Role: Dual-channel buck regulator providing tightly regulated VDDQ and VTT rails with synchronized timing and matched transient response. Use Value: Eliminates need for discrete VTT termination resistors and external reference buffers, reducing BOM count and layout area by >40%. |
Use Scenario: Supplying DDR2 memory subsystems in telecom baseband units where 1.8V VDDQ and 0.9V VTT must track within ±1.5% across temperature. IC Role / Device Role / Timing Role: Monolithic regulator generating VTT referenced to VDDQIN via VTTR buffer, ensuring ratio-metric accuracy independent of load current. Use Value: Achieves ±1.6% VTTR accuracy over –40°C to +125°C, meeting JEDEC DDR2 specification without calibration. |
| High-Density FPGA Memory Interface | Battery-Powered DDR1 Module |
Use Scenario: Powering DDR interfaces on Xilinx Kintex-7 FPGAs in space-constrained test equipment with 12V input and strict EMI limits. IC Role / Device Role / Timing Role: Interleaved dual-buck controller minimizing input ripple and enabling 2MHz operation with 1.5µH inductors. Use Value: 180° phase shift cuts input capacitor RMS current by 28%, allowing use of smaller 22µF X5R ceramics instead of 47µF tantalums. |
Use Scenario: Enabling DDR1 memory in portable medical devices powered by 3S Li-ion (10.8V–12.6V) with minimal quiescent power draw. IC Role / Device Role / Timing Role: High-efficiency dual buck with Burst Mode® on VDDQ channel and ultra-low shutdown current (<15µA). Use Value: Extends battery life by maintaining >92% peak efficiency at 2A load while drawing only 1.3mA quiescent current in active mode. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel DDR buck regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51220ARUKT | Single-chip DDR power solution with integrated MOSFETs; lower max input (5.5V); no VTTR buffer; 3A VDDQ only, 1.5A VTT | Designed for notebook DDR3; lacks independent VIN1/VIN2 inputs and 12V+ input support | Select when cost-sensitive, low-input-voltage (<6V), single-supply DDR3 designs dominate |
| ISL95812IRZ | Supports 3.3V–24V input; includes PMBus interface; higher quiescent current (2.5mA); VTTR accuracy ±2.5% over temp | Targeted at server DDR4 with telemetry; requires digital configuration; larger 32-QFN package | Select when remote monitoring, dynamic voltage scaling, or DDR4 compliance are required |
Compared with TPS51220ARUKT and ISL95812IRZ, the LTC3634EFE#PBF uniquely combines 15V input capability, ±3A dual-channel symmetric current, ±1.6% VTTR accuracy, and 180° interleaving in a thermally optimized TSSOP-making it optimal for industrial DDR3 systems with wide input range and analog precision requirements.
Availability
LTC3634EFE#PBF is available at Aetrix Electronics and suitable for DDR3 memory power supplies, FPGA memory interfaces, and battery-powered DDR2/DDR1 modules requiring stable component supply, long-term lifecycle assurance, and industrial temperature qualification.
Supply support for LTC3634EFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017, inheriting its leadership in high-performance power management ICs, precision analog, and mixed-signal solutions for demanding industrial and communications applications.
The LTC3634EFE#PBF belongs to Linear's DDR-specific power regulator family, engineered to replace multi-component discrete solutions with monolithic integration, precise voltage tracking, and robust protection for memory subsystems in mission-critical equipment.
FAQ
What is the maximum input voltage rating for the LTC3634EFE#PBF?
The LTC3634EFE#PBF has an absolute maximum input voltage rating of 16V on VIN1 and VIN2 pins, with transient overvoltage protection activating at 17.5V (rising) and releasing at 16.5V (falling). This allows safe operation from 12V rails with margin for typical supply transients. The LTC3634EFE#PBF is rated for continuous operation up to 15V, making it suitable for industrial 12V systems and automotive battery-derived supplies.
How does the VTTR output function in the LTC3634EFE#PBF?
The VTTR output of the LTC3634EFE#PBF is a buffered, low-noise reference equal to VDDQIN × 0.5, accurate to ±1.6% at 0.75V across temperature. It sources/sinks ±10mA and drives up to 0.01µF capacitive load. In the LTC3634EFE#PBF, VTTR serves as the feedback reference for Channel 2 (VTT rail), ensuring ratio-metric tracking to the VDDQIN supply-critical for DDR1/2/3 bus termination compliance. The LTC3634EFE#PBF uses this internally to regulate VTT without external components.
Can the LTC3634EFE#PBF operate with different input voltages on VIN1 and VIN2?
Yes, the LTC3634EFE#PBF supports independent input supplies: VIN1 powers Channel 1 (VDDQ) and the internal INTVCC LDO, while VIN2 powers Channel 2 (VTT) only. Both inputs accept 3.6V–15V, enabling split-rail configurations-for example, 5V for VDDQ and 12V for VTT-or shared 12V operation. This flexibility allows optimization of efficiency and noise isolation in complex DDR memory subsystems using the LTC3634EFE#PBF.
What phase shift options does the LTC3634EFE#PBF support, and how are they selected?
The LTC3634EFE#PBF supports 90° or 180° phase shift between channels via the PHMODE pin: grounding PHMODE selects 90°, tying it to INTVCC selects 180°. The 180° mode interleaves switching edges, reducing input capacitor RMS current and supply noise-especially beneficial in high-current DDR3 applications. The LTC3634EFE#PBF does not support in-phase operation; the minimum phase offset is 90°, preventing simultaneous high-current draw from the input source.
Is the LTC3634EFE#PBF pin-compatible with the QFN-packaged LTC3634 variants?
No, the LTC3634EFE#PBF in 28-lead TSSOP is not pin-compatible with the QFN-packaged LTC3634 variants (e.g., LTC3634EUFD#PBF), despite identical functionality and signal naming. Pin numbering differs between packages: TSSOP uses Pins 1–28 with exposed PGND as Pin 29, while QFN uses Pins 1–28 plus exposed PGND as Pin 29-but physical pin locations and thermal pad layout are incompatible. Layout redesign is required when substituting the LTC3634EFE#PBF for QFN versions.
LTC3634EFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Converter, DDR
- Voltage - Input:
- 1.4V ~ 15V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.6V ~ 3V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP-EP
LTC3634EFE#PBF FAQ
1.How can I place an order for LTC3634EFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3634EFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3634EFE#PBF reliable?
The price and inventory of LTC3634EFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3634EFE#PBF is usually 5 days.
3.What payment methods are accepted for LTC3634EFE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3634EFE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3634EFE#PBF?
LTC3634EFE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3634EFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3634EFE#PBF?
For technical support, including LTC3634EFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3634EFE#PBF requirements.
6.How does Aetrix verify that LTC3634EFE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3634EFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3634EFE#PBF meets industry standards.
7.What is the process for return or replacement of LTC3634EFE#PBF?
All LTC3634EFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3634EFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3634EFE#PBF part is unused and in its original packaging.
Return procedure for LTC3634EFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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