Analog Devices Inc. LTC3634HUFD#PBF
- Part No.:
- LTC3634HUFD#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 28-WFQFN Exposed Pad
- Datasheet:
-
LTC3634HUFD#PBF.pdf
- Description:
- IC REG CONV DDR 2OUT 28QFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,054
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Product details
Overview
LTC3634HUFD#PBF from Analog Devices (formerly Linear Technology) is a dual-channel monolithic synchronous step-down regulator optimized for DDR memory power delivery, providing independent VDDQ (1.8V/3A) and bidirectional VTT (0.9V/±3A) rails. It operates from 3.6V–15V input, supports 500kHz–4MHz programmable switching frequency, delivers up to 95% efficiency, and features 180° out-of-phase channel operation to reduce input RMS current ripple in server and embedded DDR1/2/3 systems.
For engineers reviewing the LTC3634HUFD#PBF datasheet, LTC3634HUFD#PBF pinout, LTC3634HUFD#PBF application, or LTC3634HUFD#PBF equivalent, key selection criteria include its ±3A per-channel sink/source capability for VTT termination, VTTR = VDDQIN/2 buffered reference (±1.6% accuracy at 0.75V), controlled on-time architecture enabling stable high-frequency operation from 12V input, and thermal-rated –40°C to 150°C junction operation in the 4mm × 5mm QFN-28 package.
Technical Context
The LTC3634HUFD#PBF implements current-mode control with valley-current limiting (±3.3A to ±5.5A) and a unique controlled on-time architecture that maintains constant frequency under wide VIN/VOUT ratios-critical for DDR applications where VDDQ and VTT must track tightly across load transients. Each channel uses independent error amplifiers: Channel 1 references an internal 0.6V bandgap, while Channel 2 references the buffered VTTR output derived from VDDQIN.
It integrates dual 130mΩ top / 65mΩ bottom MOSFETs per channel, supports external synchronization via MODE/SYNC pin, enables phase-shifted operation (90° or 180°) via PHMODE, and includes dedicated protection features including VIN overvoltage lockout (17.5V trip), overtemperature shutdown, and PGOOD status outputs with 40µs filtering to suppress transient-induced glitches.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.6V to 15V - supports direct connection to 5V or 12V system rails and battery-powered DDR subsystems. |
| Output Current Capability | ±3A per channel - enables full-swing sourcing and sinking for DDR bus termination without external FETs. |
| Switching Frequency Range | 500kHz to 4MHz - adjustable via RT resistor; higher frequencies allow smaller magnetics and capacitors in space-constrained designs. |
| VTTR Reference Accuracy | ±1.6% at 0.75V - ensures precise VTT regulation matching DDR specification requirements for VDDQ/2 tracking. |
| Thermal Rating | –40°C to 150°C junction - qualified for high-reliability industrial and extended-temperature embedded DDR applications. |
| Efficiency | Up to 95% - achieved at full load with 12V input, minimizing thermal load in dense memory modules. |
| Phase Shift Control | Selectable 90° or 180° - reduces input capacitor RMS current and supply noise when interleaving channels. |
Pinout & Package
Package: 28-lead 4mm × 5mm plastic QFN with exposed PGND pad (Pin 29), thermally enhanced for high-power DDR applications. θJA = 43°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PGOOD1 / PGOOD2 | Open-drain power-good status outputs | Assert low when respective VFB deviates >±8% from regulation point; 15mV hysteresis prevents chatter during transients. |
| PHMODE | Phase select input | Logic-low = 90° phase shift; logic-high = 180° phase shift; enables interleaved operation to reduce input ripple. |
| RUN1 / RUN2 | Channel enable inputs | Enable above 1.22V; disable below 1.01V - allows independent sequencing of VDDQ and VTT rails. |
| MODE/SYNC | Mode select & sync input | Ground = forced continuous mode; INTVCC = Burst Mode®; external clock = frequency synchronization with PLL lock. |
| VDDQIN | External reference input | Sets VTTR = VDDQIN/2; used to derive precise VTT reference from actual VDDQ voltage for tight tracking. |
| VTTR | Buffered reference output | Low-noise, ±10mA capable VDDQIN/2 reference; drives DDR VREF pins directly with <0.01µF capacitive load support. |
| ITH1 / ITH2 | Error amplifier compensation outputs | Connect external RC networks to stabilize loop response; critical for maintaining stability under fast DDR load steps. |
| SW1 / SW2 | Switch node terminals (dual) | High-side and low-side MOSFET connection points; require low-inductance layout to minimize EMI and switching losses. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent synchronous buck regulators | Enables simultaneous, separately regulated VDDQ and VTT rails with no external power devices required. |
| Controlled on-time architecture | Maintains stable 500kHz–4MHz switching frequency even at high step-down ratios (e.g., 12V→0.9V), improving transient response. |
| VTTR buffered reference output | Provides ±10mA, low-noise VDDQIN/2 reference with ±1.6% accuracy - eliminates need for external divider or buffer IC. |
| 180° out-of-phase operation | Reduces input capacitor RMS current by ~30% versus in-phase operation, lowering required bulk capacitance and supply noise. |
| Integrated protection suite | Includes VIN overvoltage lockout (17.5V), overtemperature shutdown, short-circuit protection, and filtered PGOOD outputs. |
Applications
| DDR Memory Power Supply | Server Memory Module |
|---|---|
Use Scenario: Powering DDR3 SDRAM on enterprise server DIMMs requiring strict VDDQ (1.8V) and VTT (0.9V) regulation with fast load-step response. IC Role / Device Role / Timing Role: Dual-channel buck controller delivering regulated VDDQ and bidirectional VTT termination, with VTTR reference tracking actual VDDQIN voltage. Use Value: Eliminates discrete FETs and external reference ICs; 180° interleaving cuts input ripple, allowing smaller bulk capacitors and cleaner supply rails. |
Use Scenario: High-density RDIMM/LRDIMM power delivery where thermal constraints demand high-efficiency, high-temperature operation. IC Role / Device Role / Timing Role: Primary DDR power IC managing VDDQ ramp-up, VTT tracking, and power-good sequencing per JEDEC spec. Use Value: –40°C to 150°C rating ensures reliability in thermally stressed server environments; integrated PGOOD filtering prevents false resets during memory training. |
| Industrial Embedded DDR System | Test Equipment Memory Subsystem |
Use Scenario: Ruggedized industrial controller with DDR2 memory operating in extended temperature environments (e.g., base station equipment). IC Role / Device Role / Timing Role: Dual-output regulator supplying VDDQ and VTT with independent enable (RUN1/RUN2) for controlled power sequencing. Use Value: Robust overvoltage (17.5V) and overtemperature protection ensure field reliability; VTTR accuracy meets DDR2 VREF tolerance (±1.6%). |
Use Scenario: Automated test equipment requiring fast, repeatable DDR initialization with precise voltage tracking during calibration cycles. IC Role / Device Role / Timing Role: Precision reference generator (VTTR) and tightly regulated VTT source synchronized to VDDQIN for measurement-grade signal integrity. Use Value: ±1.6% VTTR accuracy and <40µs PGOOD filter enable deterministic power-good assertion timing critical for automated test sequences. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel DDR power supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51200DRCR | Single-channel VTT sink/source IC only; requires separate VDDQ regulator; lower max input (5.5V); no VTTR buffer. | Designed for cost-sensitive client DDR3 laptops; lacks integrated VDDQ regulation and high-temp rating. | Use only when VDDQ is supplied externally and ambient temperature stays below 85°C. |
| LTC3633EUFD#PBF | Single-channel version; same architecture but no VTT/VDDQIN interface or VTTR output; rated –40°C to 125°C. | Targets general-purpose POL applications, not DDR-specific; cannot generate VTT or track VDDQIN. | Select only for non-DDR buck needs where dual-rail tracking and termination are unnecessary. |
Compared with TPS51200DRCR and LTC3633EUFD#PBF, the LTC3634HUFD#PBF uniquely integrates both VDDQ and VTT regulation with VDDQIN-tracking VTTR reference, supports 15V input for industrial 12V rail compatibility, and sustains operation up to 150°C junction-making it the sole option among these three qualified for high-reliability, thermally demanding DDR3/DDR2 server and embedded applications.
Availability
LTC3634HUFD#PBF is available at Aetrix Electronics and suitable for DDR memory power supplies, server DIMM modules, and industrial embedded systems requiring stable component supply with guaranteed long-term availability and traceable sourcing.
Supply support for LTC3634HUFD#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for all Linear power management ICs.
The LTC3634HUFD#PBF belongs to Linear's high-performance DDR power regulator family, designed specifically to replace multi-chip solutions with monolithic integration of VDDQ, VTT, and VTTR functions for DDR1/2/3 memory subsystems.
FAQ
What is the maximum allowable input voltage for the LTC3634HUFD#PBF?
The LTC3634HUFD#PBF has an absolute maximum VIN rating of 16V, with overvoltage lockout triggered at 17.5V (rising) and released at 16.5V (falling). Continuous operation is specified from 3.6V to 15V, making it compatible with standard 5V and 12V system rails while protecting against transient surges common in industrial power environments. This ensures robust operation without external clamping in most DDR applications.
How does the VTTR output function in the LTC3634HUFD#PBF?
The VTTR output of the LTC3634HUFD#PBF is a buffered, low-noise voltage equal to VDDQIN × 0.5, accurate to ±1.6% at 0.75V. It sources/sinks up to ±10mA and drives capacitive loads ≤0.01µF directly-enabling it to serve as the DDR VREF reference without external components. The LTC3634HUFD#PBF uses this same VTTR voltage as the feedback reference for Channel 2 (VTT), ensuring precise tracking to half the actual VDDQIN voltage.
Can the LTC3634HUFD#PBF operate with only one channel enabled?
Yes, the LTC3634HUFD#PBF supports independent channel control: RUN1 enables/disables Channel 1 (VDDQ), and RUN2 controls Channel 2 (VTT). Either channel can be disabled while the other remains active-allowing flexible power sequencing, such as powering VDDQ before VTT during DDR initialization. When both RUN pins are low, the device enters ultra-low-quiescent shutdown (<15µA total IQ).
What is the purpose of the PHMODE pin on the LTC3634HUFD#PBF?
The PHMODE pin on the LTC3634HUFD#PBF selects interleave phase between the two switch nodes: grounding PHMODE forces 90° phase shift, while tying it to INTVCC sets 180° phase shift. This interleaving reduces input capacitor RMS current and supply noise-particularly valuable in high-current DDR applications. The LTC3634HUFD#PBF does not support in-phase operation; 90° or 180° are the only valid configurations.
Does the LTC3634HUFD#PBF support external clock synchronization?
Yes, the MODE/SYNC pin of the LTC3634HUFD#PBF accepts an external clock signal (500kHz–4MHz) to synchronize switching frequency. An internal PLL locks the bottom-FET turn-on edge to the rising edge of the applied clock, ensuring deterministic timing. When synchronized, Channel 1 defaults to forced continuous mode, while Channel 2 remains continuously operational-maintaining stable VTT regulation during clock transitions.
LTC3634HUFD#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Converter, DDR
- Voltage - Input:
- 1.4V ~ 15V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.6V ~ 3V
- Operating Temperature:
- -40°C ~ 150°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-QFN (4x5)
LTC3634HUFD#PBF FAQ
1.How can I place an order for LTC3634HUFD#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3634HUFD#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3634HUFD#PBF reliable?
The price and inventory of LTC3634HUFD#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3634HUFD#PBF is usually 5 days.
3.What payment methods are accepted for LTC3634HUFD#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3634HUFD#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3634HUFD#PBF?
LTC3634HUFD#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3634HUFD#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3634HUFD#PBF?
For technical support, including LTC3634HUFD#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3634HUFD#PBF requirements.
6.How does Aetrix verify that LTC3634HUFD#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3634HUFD#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3634HUFD#PBF meets industry standards.
7.What is the process for return or replacement of LTC3634HUFD#PBF?
All LTC3634HUFD#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3634HUFD#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3634HUFD#PBF part is unused and in its original packaging.
Return procedure for LTC3634HUFD#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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