Analog Devices Inc. LTC3634IFE#PBF
- Part No.:
- LTC3634IFE#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC3634IFE#PBF.pdf
- Description:
- IC REG CONV DDR 2OUT 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,636
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Product details
Overview
LTC3634IFE#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, monolithic synchronous step-down regulator optimized for DDR1/DDR2/DDR3 memory power delivery. It delivers ±3A per channel across 3.6V–15V input, provides VDDQ (0.6V–3V) and VTT (VDDQIN×0.5, ±3A) rails, and features 180° out-of-phase operation to reduce input ripple - used in server DIMM modules, FPGA-based memory interfaces, and high-speed embedded controllers.
For engineers reviewing the LTC3634IFE#PBF datasheet, LTC3634IFE#PBF pinout, LTC3634IFE#PBF application, or LTC3634IFE#PBF equivalent, key selection criteria include its dual-rail DDR termination capability, VTTR reference accuracy (±1.6% at 0.75V), programmable 500kHz–4MHz switching frequency, controlled on-time architecture for stable high-frequency operation from 12V input, and thermal-enhanced TSSOP-28 package with exposed PGND pad.
Technical Context
The LTC3634IFE#PBF implements current-mode control with independent error amplifiers per channel: Channel 1 regulates VDDQ against a 0.6V internal reference, while Channel 2 regulates VTT against VTTR (VDDQIN×0.5). Its controlled on-time architecture enables fast transient response and stable operation at high duty-cycle ratios - critical for low-VOUT DDR applications.
Phase shift is hardware-selectable via PHMODE pin (90° or 180°), and synchronization is supported through MODE/SYNC pin with PLL-locked external clock input. VIN overvoltage lockout (17.5V rising, 16.5V falling) and thermal shutdown protect against system-level faults without requiring external circuitry.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.6V to 15V - supports direct connection to 5V/12V PoL rails and wide-range battery inputs. |
| Output Current per Channel | ±3A - sustains bidirectional VTT bus termination current required by DDR standards. |
| VTT Reference Accuracy | ±1.6% at 0.75V - ensures compliant VTTR tracking for DDR3 VREF specification. |
| Switching Frequency Range | 500kHz to 4MHz - adjustable via RT resistor; enables optimization of inductor size vs. efficiency. |
| Phase Shift Configuration | 90° or 180° - reduces RMS input current and eases input capacitor sizing when interleaved. |
| Thermal Protection | Junction shutdown at 150°C - protects MOSFETs during overload without external thermal sensor. |
| Package | 28-Lead TSSOP with exposed PGND pad - θJA = 25°C/W enables high-power operation without heatsink in compact layouts. |
Pinout & Package
Package: 28-Lead Plastic TSSOP (FE), thermally enhanced with exposed PGND pad soldered to PCB for low-impedance power ground and thermal dissipation (θJA = 25°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PGOOD1 (Pin 4) | Channel 1 Power Good Output | Open-drain signal pulled low if VFB1 deviates >±8% from 0.6V reference - used for system power sequencing. |
| PHMODE (Pin 5) | Phase Select Input | Logic-high (INTVCC) forces 180° out-of-phase switching between channels; logic-low enables 90° mode. |
| RUN1/RUN2 (Pins 6 & 9) | Channel Enable Inputs | Active-high enable (>1.22V); <1V disables channel - supports independent power gating of VDDQ/VTT rails. |
| MODE/SYNC (Pin 7) | Sync & Mode Control | Accepts external clock for frequency synchronization; floating/INTVCC enables Burst Mode® on Channel 1. |
| VDDQIN (Pin 13) | VTT Reference Input | External voltage source (1.5V–2.6V) defining VTTR = VDDQIN × 0.5 - enables adaptive VREF for varying DDR supply voltages. |
| VTTR (Pin 21) | Buffered Reference Output | Low-noise, ±10mA-capable output at VDDQIN×0.5 - directly drives DDR memory VREF pins without external buffer. |
| PGND (Exposed Pad) | Power Ground Return | Mandatory soldered connection to PCB ground plane - provides primary thermal path and low-inductance return for high di/dt currents. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent DDR rails | Simultaneous VDDQ (0.6V–3V) and VTT (VDDQIN×0.5, ±3A) generation from single IC - eliminates discrete regulator pairing and timing skew. |
| Controlled on-time architecture | Enables stable 12V-to-0.9V conversion at 2MHz+ without external compensation - reduces BOM count and layout sensitivity. |
| Interleaved phase operation | 180° channel phasing cuts input capacitor RMS current by ~30% - allows smaller ceramic input caps and lower supply noise. |
| Integrated VTTR buffer | ±10mA drive capability with <0.01µF capacitive load support - meets JEDEC DDR3 VREF sourcing/sinking requirements without external op-amp. |
| Robust protection suite | Includes VIN overvoltage lockout (17.5V), thermal shutdown, short-circuit protection, and PGOOD filtering (40µs) - reduces need for external fault management circuitry. |
Applications
| DDR Memory Power Supply | FPGA-Based Memory Interface |
|---|---|
Use Scenario: Powering DDR3 SDRAM on enterprise server DIMMs with strict VREF tracking and bidirectional VTT termination. IC Role / Device Role / Timing Role: Generates synchronized VDDQ and VTT rails while providing VTTR reference aligned to VDDQIN - fulfills JEDEC DDR3 power architecture requirements. Use Value: Eliminates need for separate VTT LDO + VREF buffer; ±1.6% VTTR accuracy ensures memory interface margin under temperature and load variation. |
Use Scenario: Supplying configurable memory subsystems in Xilinx Kintex/UltraScale FPGAs where VDDQ and VTT must track dynamically scaled core voltages. IC Role / Device Role / Timing Role: Dual-channel regulation with VDDQIN-referenced VTTR enables real-time adaptation to FPGA I/O bank voltage changes. Use Value: Reduces FPGA configuration complexity by removing external DACs or resistive dividers for VREF scaling - improves system-level timing closure. |
| Industrial Embedded Controller | High-Speed Data Acquisition Module |
Use Scenario: Powering DDR2 memory in ruggedized ARM-based controllers operating from 12V vehicle or 48V telecom supplies. IC Role / Device Role / Timing Role: High-efficiency step-down from wide-input range with integrated overvoltage protection - replaces multi-stage buck + LDO solutions. Use Value: 95% peak efficiency at full load extends thermal headroom in sealed enclosures; TSSOP package supports automated optical inspection (AOI). |
Use Scenario: Supporting DDR3 memory buffers in PCIe-based digitizers requiring low-noise, tightly regulated VREF for ADC/DAC reference stability. IC Role / Device Role / Timing Role: Low-noise VTTR output (<10µV RMS) serves as precision analog reference - decoupled from digital switching noise via dedicated buffer. Use Value: Enables <1 LSB INL error in 16-bit data converters by eliminating VREF drift induced by shared power domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-rail DDR power supply applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS51216RUKT | Single-channel DDR controller with external VTT FET driver; no integrated VTTR buffer; requires external 0.5× divider and op-amp. | Designed for cost-sensitive notebooks; lacks bidirectional VTT sink capability and VTTR accuracy spec. | Choose only if VTT current <±1.5A and VTTR accuracy >±3% is acceptable; adds 3–4 passive components. |
| ISL95812IRZ | Monolithic dual-channel DDR power IC with integrated VTTR buffer; ±2% VTTR accuracy; max 2.5A per channel; fixed 1.2MHz frequency. | Targeted at mobile platforms; lower current rating and no frequency programming or phase shift flexibility. | Select when board space is constrained and 2.5A VTT suffices; no RT resistor or PHMODE pin needed - simplifies layout but limits design reuse. |
Compared with TPS51216RUKT and ISL95812IRZ, the LTC3634IFE#PBF uniquely combines ±3A bidirectional VTT, ±1.6% VTTR accuracy, programmable frequency, and selectable 180° phasing - making it the only option supporting full-spec DDR3 server-grade memory power with minimal external components.
Availability
LTC3634IFE#PBF is available at Aetrix Electronics and suitable for DDR memory power supplies, FPGA I/O banks, and industrial embedded controllers requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LTC3634IFE#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance power management portfolio with rigorous automotive and industrial qualification standards.
The LTC3634IFE#PBF belongs to Linear's DDR-specific power regulator family, engineered to meet JEDEC-compliant VDDQ/VTT/VTTR sequencing, accuracy, and transient response requirements for DDR1–DDR3 memory systems.
FAQ
What is the maximum allowable input voltage for the LTC3634IFE#PBF?
The LTC3634IFE#PBF has an absolute maximum VIN rating of 16V, with overvoltage lockout activating at 17.5V (rising) and releasing at 16.5V (falling). Continuous operation above 15V violates the recommended operating range and risks permanent damage. The device is rated for 3.6V–15V input during normal operation, supporting both 5V and 12V point-of-load applications.
Does the LTC3634IFE#PBF support bidirectional current on the VTT rail?
Yes, the LTC3634IFE#PBF supports true bidirectional VTT current up to ±3A per channel, as confirmed by its valley current limit specifications (ILIM2: +3.3A to +5.5A positive, –3.3A to –5.5A negative) and typical application waveforms showing sourcing and sinking behavior. This meets DDR3 bus termination requirements where current flows into or out of the memory bus depending on data state.
How is VTTR accuracy specified for the LTC3634IFE#PBF?
The LTC3634IFE#PBF specifies VTTR accuracy as ±1.6% at 0.75V output under conditions of 1.5V < VDDQIN < 2.6V and ±10mA load. This is derived from the electrical characteristic "VTTR = 0.492•VDDQIN to 0.508•VDDQIN", yielding a ±1.6% tolerance band around the ideal 0.5× ratio - critical for DDR3 VREF compliance.
Can the LTC3634IFE#PBF operate with different input voltages on VIN1 and VIN2?
Yes, the LTC3634IFE#PBF supports independent input supplies: VIN1 powers Channel 1 (VDDQ) and the internal INTVCC regulator, while VIN2 powers Channel 2 (VTT) separately. Both inputs accept 3.6V–15V, enabling split-rail configurations - for example, 5V for VDDQ and 12V for VTT - without cross-coupling or efficiency penalty.
What package thermal performance does the LTC3634IFE#PBF offer in TSSOP?
The LTC3634IFE#PBF in FE-package (28-lead TSSOP) has a junction-to-ambient thermal resistance (θJA) of 25°C/W, significantly lower than the QFN variant's 43°C/W. This is achieved via the exposed PGND pad, which must be soldered to a large PCB copper area. At 3A load per channel and 12V input, this enables reliable operation up to 125°C ambient without forced airflow.
LTC3634IFE#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Applications:
- Converter, DDR
- Voltage - Input:
- 1.4V ~ 15V
- Number of Outputs:
- 2
- Voltage - Output:
- 0.6V ~ 3V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP-EP
LTC3634IFE#PBF FAQ
1.How can I place an order for LTC3634IFE#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3634IFE#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3634IFE#PBF reliable?
The price and inventory of LTC3634IFE#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3634IFE#PBF is usually 5 days.
3.What payment methods are accepted for LTC3634IFE#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3634IFE#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3634IFE#PBF?
LTC3634IFE#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3634IFE#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3634IFE#PBF?
For technical support, including LTC3634IFE#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3634IFE#PBF requirements.
6.How does Aetrix verify that LTC3634IFE#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3634IFE#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3634IFE#PBF meets industry standards.
7.What is the process for return or replacement of LTC3634IFE#PBF?
All LTC3634IFE#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3634IFE#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3634IFE#PBF part is unused and in its original packaging.
Return procedure for LTC3634IFE#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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