Analog Devices Inc. LTC3672BEDC-1#TRMPBF
- Part No.:
- LTC3672BEDC-1#TRMPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 8-WFDFN Exposed Pad
- Datasheet:
-
LTC3672BEDC-1#TRMPBF.pdf
- Description:
- IC REG TRIPLE BUCK/LNR SYNC 8DFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3672BEDC-1#TRMPBF from Analog Devices (formerly Linear Technology) is a monolithic triple-output power management IC integrating a 400mA synchronous buck regulator and two 150mA fixed-output LDOs in an 8-lead 2mm × 2mm DFN package. It delivers 1.8V (buck), 1.2V (LDO1), and 2.8V (LDO2) from a single 2.9V–5.5V input, supporting Li-ion/Li-Po battery-powered handheld devices with minimal external components - only one inductor, one input capacitor, and three output capacitors.
For engineers reviewing the LTC3672BEDC-1#TRMPBF datasheet, LTC3672BEDC-1#TRMPBF pinout, LTC3672BEDC-1#TRMPBF application, or LTC3672BEDC-1#TRMPBF equivalent, key selection considerations include its constant-frequency 2.25MHz operation, ±2.5% output voltage accuracy, internal soft-start per rail, and shared enable control for all three outputs - critical for compact, low-noise multivoltage systems in space-constrained portable electronics.
Technical Context
The LTC3672BEDC-1#TRMPBF employs current-mode control in its 2.25MHz buck stage, enabling fast line/load transient response and stable discontinuous conduction mode at light loads. Its BUCKOUT pin provides direct feedback sensing, while internal compensation eliminates external loop components.
LDO1 accepts power from either VIN or the buck output (VIN1), enabling efficiency optimization by cascading regulation - e.g., stepping 3.6V → 1.8V (buck, ~85% eff.) → 1.2V (LDO1, ~67% eff.), achieving ~57% overall efficiency versus ~33% with direct linear conversion. LDO2 draws directly from VIN and features 188–250mV dropout at 150mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.9V to 5.5V - matches single-cell Li-ion/Li-Po battery operating range including full charge (4.2V) and discharge cutoff (~3.0V). |
| Buck Output | Fixed 1.8V ±2.5%, 400mA max - powers core logic or I/O rails of FPGAs, ASICs, or microcontrollers requiring tight regulation. |
| LDO1 Output | Fixed 1.2V ±2.5%, 150mA max, dropout 484–570mV - supports low-voltage digital cores when powered from buck output. |
| LDO2 Output | Fixed 2.8V ±2.5%, 150mA max, dropout 188–250mV - supplies RF front-end bias or analog sensors needing stable mid-rail voltage. |
| Switching Frequency | 2.25MHz (±250kHz) - enables use of small 4.7μH inductors and ceramic capacitors, reducing solution footprint and EMI filtering burden. |
| Quiescent Current | 260μA (VIN, all outputs enabled, no load) - extends battery runtime in always-on or low-power standby modes. |
| Package | 8-lead 2mm × 2mm × 0.75mm DFN with exposed pad - provides low thermal resistance (θJC = 20°C/W) for high-power-density designs. |
Pinout & Package
Package: 8-lead plastic DFN (2mm × 2mm × 0.75mm) with exposed thermal pad (Pin 9, GND). The exposed pad must be soldered to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SW (Pin 1) | Buck switch node | Connects to inductor; carries high di/dt switching current - requires short, low-inductance PCB trace to minimize EMI. |
| GND (Pin 2) | Power ground reference | Main return path for buck and LDO currents; connects to exposed pad for lowest impedance. |
| ENALL (Pin 3) | Global enable input | CMOS-compatible logic input (VIH ≥ 1.2V, VIL ≤ 0.4V); internal 5.5MΩ pulldown ensures default shutdown. |
| BUCKOUT (Pin 4) | Buck feedback sense | Connects to buck output capacitor; sets regulation point via internal 800mV reference and resistor divider (not required - fixed output). |
| VIN1 (Pin 5) | LDO1 input supply | Accepts 1.8V (from buck) or up to VIN; determines LDO1 efficiency and dropout margin - critical for cascade configuration. |
| LDO1 (Pin 6) | LDO1 regulated output | 1.2V output; requires ≥1μF ceramic bypass capacitor to ground for stability and transient response. |
| LDO2 (Pin 7) | LDO2 regulated output | 2.8V output; requires ≥1μF ceramic bypass capacitor to ground; dropout limited by VIN–VOUT differential. |
| VIN (Pin 8) | Main input supply | Provides power to buck regulator, LDO2, and IC bias; requires ≥2.2μF ceramic bypass capacitor to handle high-frequency AC current. |
Key Features
| Feature | Design Value |
|---|---|
| Triple integrated regulation | Single-chip solution replaces three discrete regulators - reduces BOM count, PCB area, and design validation effort. |
| Shared enable control | One ENALL pin sequences all three outputs on/off simultaneously - simplifies power sequencing and eliminates need for external supervisors. |
| Internal soft-start | 200μs (buck), 300μs (LDO1), 100μs (LDO2) - prevents inrush current during startup, protecting input source and output capacitors. |
| Switch node slew-rate control | Patent-pending circuitry limits dV/dt on SW pin - reduces radiated EMI without compromising efficiency or transient response. |
| Light-load cycle-skipping | Maintains 2.25MHz regulation down to very light loads, then skips cycles to sustain efficiency - avoids low-frequency beat notes in audio-sensitive applications. |
Applications
| Mobile Handset Power | Portable Media Player |
|---|---|
|
Use Scenario: Powering baseband processor (1.8V core), memory I/O (1.2V), and RF transceiver bias (2.8V) from a single Li-Po cell. IC Role / Device Role / Timing Role: Central power management unit delivering sequenced, low-noise, multivoltage rails with shared enable and minimal footprint. Use Value: Eliminates need for three separate regulators and associated passives, reducing solution size by >40% versus discrete implementation. |
Use Scenario: Supplying FPGA core (1.2V), I/O bank (1.8V), and display backlight driver (2.8V) in a PMP with tight height constraints. IC Role / Device Role / Timing Role: Compact triple-output PMIC enabling single-layer routing and thin-profile PCB stackup (≤1.0mm total height). Use Value: 2mm × 2mm DFN package and 2.25MHz switching allow use of 1.2mm-height inductors and 0.5mm-thick capacitors. |
| GPS Navigation Device | FPGA/CPLD Development Board |
|
Use Scenario: Providing clean, low-noise 1.8V (GPS baseband), 1.2V (RF front-end LNA), and 2.8V (GNSS antenna module) from a 3.7V battery. IC Role / Device Role / Timing Role: Low-EMI power source with slew-rate controlled SW pin and ceramic-capacitor-only design minimizing conducted noise into sensitive RF paths. Use Value: Measured EMI reduction enables compliance with CISPR-22 Class B without ferrite beads or shielding cans. |
Use Scenario: Generating multiple logic-supply rails (1.2V core, 1.8V I/O, 2.8V transceiver) for prototyping FPGA-based industrial controllers. IC Role / Device Role / Timing Role: Reference power solution with known performance, fixed outputs, and documented transient response (see TA04b load step test). Use Value: Pre-characterized load step behavior (100mA LDO2 + 10mA LDO1) allows accurate power integrity simulation before PCB spin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output PMIC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3445EUF#PBF | I²C-programmable buck (600mA) + dual 50mA LDOs in 4mm × 4mm QFN; higher buck current but lower LDO current. | Requires firmware control and external EEPROM for configuration; suited for designs needing dynamic voltage scaling. | Select LTC3445EUF#PBF only if programmability justifies larger package and added software complexity. |
| LTC3541EDD-1#TRMPBF | Single 500mA buck + 300mA VLDO in 3mm × 3mm DFN; lacks second independent LDO. | Cannot independently supply 1.2V and 2.8V rails - requires external LDO or voltage divider for third rail. | Choose LTC3541EDD-1#TRMPBF only when system needs only two regulated outputs and higher buck current is prioritized. |
Compared with LTC3445EUF#PBF and LTC3541EDD-1#TRMPBF, the LTC3672BEDC-1#TRMPBF offers fixed, optimized triple-rail output without programming overhead or external components, making it ideal for cost-sensitive, high-volume portable devices where layout area and BOM simplicity are critical.
Availability
LTC3672BEDC-1#TRMPBF is available at Aetrix Electronics and suitable for mobile handsets, portable media players, GPS navigation devices, and FPGA development boards requiring stable component supply across production lifecycles.
Supply support for LTC3672BEDC-1#TRMPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its precision analog and power management product lines with full technical documentation and long-term support.
The LTC3672B family was designed specifically for space-constrained, battery-powered portable electronics requiring efficient, low-noise, multivoltage power delivery from a single Li-ion cell - emphasizing minimal external components and robust transient response.
FAQ
What is the maximum supported load current for each output of the LTC3672BEDC-1#TRMPBF?
The LTC3672BEDC-1#TRMPBF delivers up to 400mA from its buck output (VOUT1 = 1.8V), 150mA from LDO1 (VOUT2 = 1.2V), and 150mA from LDO2 (VOUT3 = 2.8V). Note that buck output current remains 400mA even when both LDOs are fully loaded, provided VIN1 is tied to VIN rather than the buck output - this configuration avoids current derating due to LDO1's input limitation.
Can LDO1 of the LTC3672BEDC-1#TRMPBF be powered from the buck output to improve system efficiency?
Yes, LDO1 (Pin 5, VIN1) can be connected directly to the buck output (VOUT1 = 1.8V) to form a cascaded regulation path. This configuration improves overall efficiency - for example, deriving 1.2V from a 3.6V input yields ~57% efficiency versus ~33% with direct linear conversion - because the bulk voltage step-down occurs in the higher-efficiency buck stage.
What are the required external components for basic operation of the LTC3672BEDC-1#TRMPBF?
The LTC3672BEDC-1#TRMPBF requires only seven passive components for full operation: one 4.7μH inductor (SW to VOUT1), one 2.2μF ceramic capacitor on VIN, one 10μF ceramic capacitor on VOUT1, and one 1μF ceramic capacitor each on LDO1, LDO2, and VIN1. No external compensation or feedback resistors are needed - all regulation is factory-trimmed and internally compensated.
How does the LTC3672BEDC-1#TRMPBF manage EMI in noise-sensitive applications like GPS receivers?
The LTC3672BEDC-1#TRMPBF incorporates patent-pending switch node (SW pin) slew-rate control that limits dV/dt during transitions, significantly reducing high-frequency radiated EMI. Combined with 2.25MHz constant-frequency operation and ceramic-only output filtering, this enables CISPR-22 Class B compliance without additional shielding or ferrite components - critical for integration near RF front-ends.
What is the recommended PCB layout practice for thermal management of the LTC3672BEDC-1#TRMPBF?
For optimal thermal performance, the exposed pad (Pin 9) of the LTC3672BEDC-1#TRMPBF must be soldered to a large, low-thermal-resistance PCB ground plane using ≥4 thermal vias (0.3mm diameter, spaced ≤1mm apart). This achieves θJC = 20°C/W, allowing continuous 400mA buck operation at 85°C ambient without derating - verified in Linear's DC8 package thermal characterization report.
LTC3672BEDC-1#TRMPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 8-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (2)
- Number of Outputs:
- 3
- Frequency - Switching:
- 2.25MHz
- Voltage/Current - Output 1:
- 1.8V, 400mA
- Voltage/Current - Output 2:
- 1.2V, 150mA
- Voltage/Current - Output 3:
- 2.8V, 150mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- No
- Voltage - Supply:
- 2.9V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DFN (2x2)
LTC3672BEDC-1#TRMPBF FAQ
1.How can I place an order for LTC3672BEDC-1#TRMPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3672BEDC-1#TRMPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3672BEDC-1#TRMPBF reliable?
The price and inventory of LTC3672BEDC-1#TRMPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3672BEDC-1#TRMPBF is usually 5 days.
3.What payment methods are accepted for LTC3672BEDC-1#TRMPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3672BEDC-1#TRMPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3672BEDC-1#TRMPBF?
LTC3672BEDC-1#TRMPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3672BEDC-1#TRMPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3672BEDC-1#TRMPBF?
For technical support, including LTC3672BEDC-1#TRMPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3672BEDC-1#TRMPBF requirements.
6.How does Aetrix verify that LTC3672BEDC-1#TRMPBF is sourced from the original manufacturer or authorized distributors?
All LTC3672BEDC-1#TRMPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3672BEDC-1#TRMPBF meets industry standards.
7.What is the process for return or replacement of LTC3672BEDC-1#TRMPBF?
All LTC3672BEDC-1#TRMPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3672BEDC-1#TRMPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3672BEDC-1#TRMPBF part is unused and in its original packaging.
Return procedure for LTC3672BEDC-1#TRMPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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