My Inquiry
My Account
Analog Devices Inc. LTC3722IGN-2
- Part No.:
- LTC3722IGN-2
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 24-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
LTC3722IGN-2.pdf
- Description:
- IC POWER MANAGEMENT
- Quantity:
- Payment:
- Shipping:
Inventory:2,406
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3722IGN-2 from Analog Devices is a voltage-mode, phase-shift PWM controller for zero-voltage-switched (ZVS) full-bridge DC/DC converters. It delivers adaptive and fixed ZVS control, 50mA synchronous rectifier drivers (OUTE/OUTF), 5V reference output (±1.5% initial accuracy), and operates from –40°C to 85°C in a 24-pin SSOP package. Used in telecom infrastructure power supplies delivering up to 240W at 12V output.
For engineers reviewing the LTC3722IGN-2 datasheet, LTC3722IGN-2 pinout, LTC3722IGN-2 application, or LTC3722IGN-2 equivalent, key selection factors include ZVS delay programmability via ADLY/PDLY pins, SBUS-based adaptive line sensing, UVLO hysteresis tuning via external resistor divider, and compatibility with external gate drivers like LTC4440 and LTC3901.
Technical Context
The LTC3722IGN-2 implements voltage-mode control with internal RAMP input referenced to SBUS, enabling precise phase modulation without slope compensation circuitry. Its adaptive ZVS logic monitors SBUS voltage to dynamically adjust active/passive leg delays, while fixed-mode operation supports secondary-side control when SBUS = VREF.
It integrates six 50mA output drivers (OUTA–OUTF) with programmable turn-off timing (SPRG), 5V/5mA reference (VREF), 10.25V VCC UVLO with 4.2V hysteresis, and cycle-by-cycle current limiting triggered at 300mV on CS pin. All functions operate with quiescent current as low as 5mA and start-up current of 145µA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Oscillator Frequency | 250kHz typical (CT = 270pF); sets base switching frequency for full-bridge primary drive |
| VREF Output Accuracy | ±1.5% over temperature; provides stable bias for external resistive dividers and gate driver references |
| VCC UVLO Threshold | 10.5V turn-on / 6.3V turn-off; ensures reliable startup and brownout protection across input transients |
| Output Driver Current | ±50mA per channel (OUTA–OUTF); drives high-side and synchronous rectifier gate drivers without external buffers |
| System UVLO Programmability | 5.0V threshold with 10µA hysteresis current; enables precise system-level power sequencing via resistor divider |
| Phase Shift Range | 0% to 98.5% (COMP = 0V to 4.5V); directly controls duty cycle and power delivery in ZVS full-bridge topology |
| Start-Up Current | 145µA max; minimizes auxiliary supply burden during cold-start in high-reliability telecom systems |
Pinout & Package
Package: 24-lead narrow plastic SSOP (GN), RoHS-compliant, –40°C to 85°C operating junction temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SYNC (1) | Oscillator synchronization I/O | Accepts CMOS/TTL pulses; output frequency = ½ SYNC input; enables multi-phase interleaving |
| DPRG (2) | ZVS maximum delay programming | Resistor-to-VREF sets upper limit on passive-leg turn-on delay; prevents excessive dead-time |
| RAMP (2) | Voltage-mode phase modulator input | Internally level-shifted by 650mV; carries sawtooth ramp for comparator-based duty control |
| CS (3) | Current sense comparator input | 300mV pulse-by-pulse limit threshold; feeds error amplifier and overload protection |
| COMP (4) | Error amplifier output & phase modulator input | Drives phase shift via voltage level; 70dB open-loop gain ensures tight regulation loop stability |
| FB (6) | Feedback node for output voltage regulation | 1.204V nominal reference; connects to transformer secondary feedback network |
| PDLY (9) | Passive leg ZVS delay control | Voltage divider from VIN sets fixed delay; 1.5V → 100ns, 2.25V → 220ns (RDPRG = 60.4kΩ) |
| SBUS (10) | Line voltage sense for adaptive ZVS | 1.5V at nominal VIN enables automatic delay adjustment; tied to VREF for fixed-mode operation |
| ADLY (11) | Active leg ZVS delay control | Same scaling as PDLY; decouples active-leg timing from passive-leg for asymmetric load handling |
| UVLO (12) | System undervoltage lockout input | 5.0V threshold with programmable hysteresis; sources 10µA to set turn-off point |
| SPRG (13) | Synchronous rectifier turn-off timing | Resistor-to-GND sets OUTF/OUTE turn-off delay; avoids shoot-through in secondary-side rectification |
| VREF (14) | 5V precision reference output | ±1.5% accuracy, 5mA load capability; powers external circuits and feedback dividers |
| OUTF (15) | Synchronous rectifier driver (OUTB/OUTC) | 50mA sink/source; drives low-side SR FETs on secondary side with programmable timing |
| OUTE (16) | Synchronous rectifier driver (OUTA/OUTD) | 50mA sink/source; complements OUTF for full secondary-side synchronous rectification |
| OUTD (17) | Full-bridge passive leg low-side driver | 50mA sink/source; drives MB MOSFET; referenced to PGND |
| VCC (18) | Main supply input & shunt regulator | 10.25V UVLO; self-regulates at 10.3V; supports 6V–10V operation after startup |
| OUTC (19) | Full-bridge active leg high-side driver | 50mA sink/source; drives MC MOSFET; requires external high-side gate driver |
| OUTB (20) | Full-bridge passive leg low-side driver | 50mA sink/source; drives MB MOSFET; referenced to PGND |
| OUTA (21) | Full-bridge passive leg high-side driver | 50mA sink/source; drives MA MOSFET; requires external high-side gate driver |
| PGND (22) | Power ground reference | Return path for all output drivers; must be connected directly to ceramic VCC bypass cap |
| GND (23) | Analog/substrate ground | Reference for FB, COMP, UVLO, and internal analog blocks; separate from PGND for noise isolation |
| CT (24) | Oscillator timing capacitor | 270pF ceramic sets 250kHz frequency; low ESR required for stable ramp generation |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive ZVS with DirectSense™ technology | Monitors SBUS voltage to auto-adjust ADLY/PDLY delays-eliminates manual trim and improves efficiency across 10–100% load |
| Fixed ZVS mode via SBUS = VREF | Enables secondary-side control architecture; removes dependency on primary-side voltage sensing for isolated designs |
| Integrated 5V reference with ±1.5% accuracy | Stabilizes feedback dividers and external gate drivers; reduces BOM count vs. discrete reference ICs |
| Programmable synchronous rectifier timing (SPRG) | Single resistor sets OUTF/OUTE turn-off delay-prevents cross-conduction in center-tapped secondary topologies |
| Voltage-mode control (LTC3722-2 variant) | No external slope compensation needed; simplifies design vs. current-mode controllers requiring R-C networks |
| Low 145µA start-up current | Reduces auxiliary supply requirements in standby-critical telecom systems; enables direct connection to hold-up capacitors |
Applications
| Telecom Rectifier Modules | Server PSU Front-End |
|---|---|
Use Scenario: 48V input, 12V/20A output telecom rectifier operating in hot-swap chassis with strict efficiency mandates. IC Role / Device Role / Timing Role: LTC3722IGN-2 configures full-bridge primary with adaptive ZVS and synchronizes secondary-side rectifiers via OUTE/OUTF. Use Value: Achieves >94% peak efficiency at 240W by eliminating body-diode conduction loss through precise ZVS timing. |
Use Scenario: 36–72V input, 12V/20A intermediate bus converter in modular server power supply with PMBus interface. IC Role / Device Role / Timing Role: LTC3722IGN-2 manages phase-shifted full-bridge primary and interfaces with digital controller via FB/SS/UVLO for sequencing. Use Value: Enables <100ms soft-start and hiccup-mode fault recovery-meets ATX and Open Compute Project reliability requirements. |
| Distributed Power Architecture | Industrial Isolated DC/DC |
Use Scenario: 48V backplane powering multiple 12V point-of-load regulators in industrial automation rack. IC Role / Device Role / Timing Role: LTC3722IGN-2 implements ZVS full-bridge with fixed-mode operation (SBUS = VREF) for predictable timing in distributed control. Use Value: Reduces EMI by 8dB via controlled ZVS transitions-simplifies compliance with CISPR 22 Class B emissions limits. |
Use Scenario: 36–72V input, 12V/15A isolated DC/DC for PLC I/O modules requiring reinforced insulation and -40°C startup. IC Role / Device Role / Timing Role: LTC3722IGN-2 provides robust ZVS control with UVLO hysteresis tuned for wide-input industrial rails. Use Value: Guarantees reliable startup down to -40°C using 145µA start-up current and 10.5V VCC UVLO-no auxiliary bias needed. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar full-bridge ZVS controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| UCC3895DR | Voltage-mode controller with programmable dead-time; no integrated VREF or synchronous rectifier drivers | Requires external 5V reference and gate drivers for SR FETs; lacks adaptive ZVS sensing | Choose UCC3895DR only if legacy design reuse or cost sensitivity outweighs need for integrated ZVS and SR timing |
| LTC3722IGN-1 | Peak current-mode variant with programmable slope compensation and leading-edge blanking (RLEB) | Better transient response under dynamic load steps; requires RLEB resistor and slope-compensation network | Select LTC3722IGN-1 when fast line/load regulation is critical and board space allows extra components |
Compared with UCC3895DR, LTC3722IGN-2 reduces component count by integrating VREF, SR drivers, and adaptive ZVS sensing; compared with LTC3722IGN-1, it eliminates slope compensation design effort but trades off some current-loop bandwidth.
Availability
LTC3722IGN-2 is available at Aetrix Electronics and suitable for telecom rectifier modules, server PSU front-ends, and industrial isolated DC/DC converters requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant manufacturing.
Supply support for LTC3722IGN-2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices (ADI) is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and power management markets.
The LTC3722 family was designed specifically for high-efficiency, zero-voltage-switched full-bridge DC/DC converters in telecom and server power applications where thermal performance and reliability are critical.
FAQ
What is the function of the SBUS pin on the LTC3722IGN-2?
The SBUS pin on the LTC3722IGN-2 serves as the line voltage sense input for adaptive ZVS control. When connected to a resistor divider from VIN, it scales the input voltage to 1.5V at nominal conditions, allowing the LTC3722IGN-2 to dynamically adjust ADLY and PDLY delays. If tied directly to VREF, the LTC3722IGN-2 enters fixed ZVS mode-enabling secondary-side control architectures without primary-side sensing.
How does the LTC3722IGN-2 differ from the LTC3722IGN-1 in terms of control architecture?
The LTC3722IGN-2 uses voltage-mode control with an internal RAMP input, eliminating the need for external slope compensation. In contrast, the LTC3722IGN-1 employs peak current-mode control with programmable slope compensation and leading-edge blanking (via RLEB). This makes the LTC3722IGN-2 simpler to stabilize in feedback loops but less responsive to rapid load transients than the LTC3722IGN-1.
Can the LTC3722IGN-2 drive MOSFET gates directly, or does it require external gate drivers?
The LTC3722IGN-2 provides six 50mA output drivers (OUTA–OUTF) optimized for interfacing with external gate driver ICs-not for direct high-capacitance MOSFET gate driving. OUTA/OUTC require high-side gate drivers (e.g., LTC4440), while OUTB/OUTD are ground-referenced. OUTE/OUTF drive synchronous rectifiers on the secondary side and also interface with dedicated SR drivers like LTC3901.
What is the purpose of the SPRG pin on the LTC3722IGN-2?
The SPRG pin on the LTC3722IGN-2 sets the turn-off delay for synchronous rectifier drivers OUTF and OUTE. A resistor from SPRG to GND programs this delay-critical for preventing shoot-through in center-tapped or full-wave synchronous rectifier topologies. Typical values range from 10kΩ to 100kΩ, yielding delays from ~100ns to ~300ns, ensuring safe commutation between primary and secondary-side switches.
Does the LTC3722IGN-2 support synchronization with other controllers, and how is it implemented?
Yes, the LTC3722IGN-2 supports oscillator synchronization via the SYNC pin (Pin 1). It accepts CMOS/TTL-compatible input pulses and outputs a synchronized clock at half the input frequency. This enables interleaved multi-phase full-bridge operation-reducing input/output ripple and improving thermal distribution. The SYNC threshold is 1.9V, and minimum pulse width is 75ns, verified in production testing.
LTC3722IGN-2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 24-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Output Type:
- Transistor Driver
- Function:
- Step-Up/Step-Down
- Output Configuration:
- Positive, Isolation Capable
- Topology:
- Full-Bridge
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 3.8V ~ 10.25V
- Frequency - Switching:
- -
- Duty Cycle (Max):
- 98.5%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- Yes
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Ramp, Soft Start
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SSOP
LTC3722IGN-2 FAQ
1.How can I place an order for LTC3722IGN-2 through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3722IGN-2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3722IGN-2 reliable?
The price and inventory of LTC3722IGN-2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3722IGN-2 is usually 5 days.
3.What payment methods are accepted for LTC3722IGN-2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3722IGN-2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3722IGN-2?
LTC3722IGN-2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3722IGN-2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3722IGN-2?
For technical support, including LTC3722IGN-2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3722IGN-2 requirements.
6.How does Aetrix verify that LTC3722IGN-2 is sourced from the original manufacturer or authorized distributors?
All LTC3722IGN-2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3722IGN-2 meets industry standards.
7.What is the process for return or replacement of LTC3722IGN-2?
All LTC3722IGN-2 units undergo pre-shipment inspection (PSI). If there is an issue with LTC3722IGN-2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3722IGN-2 part is unused and in its original packaging.
Return procedure for LTC3722IGN-2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3722IGN-2 Tags
-
UCC28C45DR
Texas Instruments
-
UCC28C40DR
Texas Instruments
-
UCC28C43DR
Texas Instruments
-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments
-
MIC2102YML-TR
Microchip Technology
-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments
-
LM5155DSSR
Texas Instruments
-
LM25085MYX/NOPB
Texas Instruments
-
UCC2813DTR-0
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
