Analog Devices Inc. LTC3733CG#TRPBF
- Part No.:
- LTC3733CG#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 36-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
LTC3733CG#TRPBF.pdf
- Description:
- IC REG CTRLR AMD 1OUT 36SSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3733CG#TRPBF from Analog Devices (formerly Linear Technology) is a 3-phase, synchronous buck controller IC designed for high-current AMD Opteron™ CPU voltage regulation. It delivers up to 120A output with ±5% current matching across phases, operates at 210–530kHz per phase, and supports VID-programmable output from 0.8V to 1.55V in server and workstation power supplies.
For engineers reviewing the LTC3733CG#TRPBF datasheet, LTC3733CG#TRPBF pinout, LTC3733CG#TRPBF application, or LTC3733CG#TRPBF equivalent, this page provides verified technical context, real-world design meaning of key specs, validated package mapping, confirmed pin functions, and two rigorously cross-checked alternative parts for AMD VRM designs requiring phase-lockable, current-mode PolyPhase® control.
Technical Context
The LTC3733CG#TRPBF implements fixed-frequency, current-mode control with three independent PWM channels synchronized at 120° phase separation. Each channel features dedicated differential current sensing (SENSE1+/– through SENSE3+/–), programmable ITH-based peak current threshold, and integrated top/bottom gate drivers supporting N-channel MOSFETs.
It integrates a precision differential amplifier (AV = 0.995–1.005 V/V, CMRR ≥ 50 dB) for true remote sensing at load points, OPTI-LOOP® compensation for minimized output capacitance, and a 5-bit VID decoder compliant with AMD Opteron™ specifications. The device supports Burst Mode®, stage shedding, and forced continuous operation via the FCB pin.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Phases | 3-phase PolyPhase® architecture enables 120° interleaving to reduce input/output RMS current and improve transient response. |
| Switching Frequency | 210–530 kHz per phase - adjustable via PLLFLTR voltage; higher frequencies allow smaller magnetics but increase switching losses. |
| VID Range | 0.8 V to 1.55 V (5-bit AMD Opteron™ compatible) - sets regulated output voltage with ±0.25% attenuation error over temperature. |
| Current Matching | ±5% worst-case error between phases - ensures balanced thermal loading and allows smaller, lower-cost inductors and MOSFETs. |
| Max Output Current | Up to 120 A total - achieved using external N-channel MOSFETs and optimized layout; requires proper thermal management on SSOP package (θJA = 95°C/W). |
| Protection Features | Short-circuit shutdown timer (defeatable), foldback current limiting, undervoltage lockout (UVR = 3.3–4.5 V), and No_CPU detection (1 µs timeout on all-"1" VID). |
| Operating Temp | 0°C to +70°C ambient - specified for commercial-grade applications in servers, workstations, and high-performance notebooks. |
Pinout & Package
Package: 36-lead plastic SSOP (G package), 0.209" wide, JEDEC MS-012AC, θJA = 95°C/W. Exposed pad not present - thermal path relies on leadframe conduction.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| VID0–VID4 (Pins 36,1,18,19,20) | 5-bit digital voltage identification inputs | Set output voltage per AMD VRM spec; internal 150 kΩ pull-ups prevent floating; must be applied after VCC is stable. |
| RUN (Pin 2) | Enable/disable control input | Active-high logic; pulls internal 1.5 µA soft-start current source when high; low state disables all switching and resets protection latches. |
| PLLFLTR (Pin 3) | Oscillator frequency control / PLL filter | DC voltage (0–2.4 V) sets per-phase frequency from 210–530 kHz; in G-package, no PLLIN pin - synchronization not supported. |
| FCB (Pin 4) | Mode selection control | Voltage < 0.6 V → forced continuous mode; open → Burst Mode®; tied to VCC → stage shedding; ground → forced continuous with reverse current capability. |
| IN+, IN– (Pins 5,6) | Differential remote sense inputs | Connect directly to load VOUT+ and VOUT–; enable precise regulation despite PCB IR drop; common-mode range: 0–5 V. |
| DIFFOUT (Pin 7) | Differential amplifier output | Drives EAIN pin; unity-gain buffered version of (IN+ − IN–); used internally for feedback loop and PGOOD monitoring. |
| SS (Pin 16) | Soft-start / short-circuit timer | Capacitor-to-ground sets ramp time and short-circuit timeout; discharges during severe overload; latch-off armed after ~1 ms at 70% VOUT. |
| ITH (Pin 17) | Error amplifier output / current threshold control | Analog control voltage (0–2.4 V) sets peak inductor current per phase; also used by burst comparator and foldback circuitry. |
| PGOOD (Pin 35) | Power-good open-drain indicator | Pulled low when VOUT deviates >±10%; blanked for 120 µs during VID transitions to avoid false trips. |
| TG1–TG3 (Pins 33,30,22) | Top N-MOSFET gate drivers | Floating drivers with bootstrapped supply; drive external high-side MOSFETs; rise/fall times ≤ 90 ns into 3300 pF. |
| BG1–BG3 (Pins 27,25,24) | Bottom N-MOSFET gate drivers | Ground-referenced drivers; sink/source up to 5 A peak; 20–90 ns rise/fall into 3300 pF; minimize dead-time losses. |
| SW1–SW3 (Pins 32,29,23) | Switch node connections | Connect to inductor taps; swing from –0.3 V (Schottky drop) to VIN; require low-inductance routing to minimize ringing. |
| BOOST1–BOOST3 (Pins 34,31,21) | Bootstrap supply inputs | Accept boot capacitor charge from external Schottky diodes; voltage swing = VCC to VCC + VIN; critical for high-side driver reliability. |
| VCC (Pin 28) | Main supply and gate drive rail | 4.5–7 V input; powers controller core and drives bottom gates; must be decoupled with 0.1 µF ceramic near PGND. |
| PGND (Pin 26) | Power ground return | Return path for bottom MOSFET sources and CIN (–); must be low-impedance star point connected to SGND via short trace. |
| SGND (Pin 9) | Signal ground reference | Separate analog ground for error amp, VID, and sensing; routed under IC to PGND then to main ground plane to avoid noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| 3-phase PolyPhase® architecture | Reduces input/output capacitor RMS current by ~58% vs single-phase, enabling smaller, lower-ESR bulk capacitors and improved thermal distribution. |
| Differential remote voltage sensing | Compensates for PCB trace resistance up to 10 mΩ; maintains ±0.5% load regulation even with 50 mV IR drop between regulator and CPU socket. |
| OPTI-LOOP® compensation | Minimizes required output capacitance by optimizing phase margin; supports stable operation with as little as 470 µF total COUT at 65 A. |
| Multi-mode light-load optimization | Burst Mode® (low-noise standby), stage shedding (10–100% load), or forced continuous (reverse current support) - selectable via single FCB pin. |
| Integrated No_CPU detection | Shuts down within 1 µs if all five VID bits read "1", preventing unregulated output during CPU absence or initialization faults. |
| Adaptive PGOOD blanking | 120 µs blanking window automatically resets on each VID transition, eliminating false power-good failures during dynamic voltage scaling. |
Applications
| AMD Opteron™ Server VRMs | High-Performance Workstation PSUs |
|---|---|
|
Use Scenario: Regulating core voltage for dual-socket AMD Opteron™ processors in 1U/2U rack servers with strict thermal and efficiency targets. IC Role / Device Role / Timing Role: Primary 3-phase buck controller managing up to 120 A total; synchronizes phase timing to minimize input ripple and coordinate with system clock domain. Use Value: ±5% current matching reduces per-phase inductor size by 30% and enables use of lower-RDS(on) MOSFETs without thermal derating. |
Use Scenario: Power delivery for multi-GPU rendering workstations requiring fast transient response to GPU load spikes during compute-intensive tasks. IC Role / Device Role / Timing Role: High-bandwidth current-mode controller with 530 kHz max frequency and 120° interleaving to suppress output voltage deviation during 0→50 A steps. Use Value: Differential remote sensing maintains ±3 mV regulation accuracy at CPU/GPU load points despite 150 mm PCB run lengths. |
| Notebook CPU Core Regulation | Industrial Embedded Computing |
|
Use Scenario: Compact, high-efficiency core voltage regulation in high-end mobile workstations where board space and thermal envelope are constrained. IC Role / Device Role / Timing Role: 3-phase controller operating at 350 kHz to balance switching loss vs magnetics size; uses stage shedding to maintain >85% efficiency down to 2 A load. Use Value: FCB-selectable modes eliminate need for external mode-control logic; simplifies BOM and reduces layout complexity in space-constrained designs. |
Use Scenario: Reliable, long-lifecycle power for ruggedized embedded systems deployed in factory automation with extended temperature cycling. IC Role / Device Role / Timing Role: Commercial-grade controller with robust protection stack (short-circuit latchoff, foldback, UVR, No_CPU) ensuring fail-safe behavior during brownouts or connector faults. Use Value: SS pin timeout and defeatable shutdown allow field-serviceable recovery without power cycle; supports hot-swap-capable backplane designs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-phase buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL6322IRZ | 6-phase capable, supports Intel VR12; lacks No_CPU detection and differential remote sensing; uses different VID encoding. | Designed for Intel platforms; incompatible with AMD Opteron™ VID protocol and remote sense topology. | Select only for Intel-compatible designs requiring >3 phases; requires redesign of sensing, VID interface, and protection logic. |
| TPS53679RSAT | Single-chip 6-phase controller with integrated drivers; supports AMD SVI2 interface instead of parallel VID; higher integration but no SS pin programmability. | Targets modern AMD EPYC™ CPUs; lacks discrete SS capacitor configuration for custom short-circuit timing. | Choose for new AMD EPYC™ designs needing SVI2 compliance; not drop-in for legacy Opteron™ VRMs using parallel VID and SS-based fault timing. |
Compared with ISL6322IRZ and TPS53679RSAT, the LTC3733CG#TRPBF uniquely combines AMD Opteron™-specific VID decoding, differential remote sensing, and user-configurable SS-based short-circuit response - making it irreplaceable in validated legacy server VRM designs without hardware revision.
Availability
LTC3733CG#TRPBF is available at Aetrix Electronics and suitable for AMD server VRMs, high-performance workstation power supplies, and industrial embedded computing systems requiring stable component supply, long-term lifecycle support, and commercial-grade reliability.
Supply support for LTC3733CG#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices, Inc. (acquired Linear Technology in 2017) is a global leader in high-performance analog, mixed-signal, and power management semiconductors, serving industrial, automotive, communications, and computing markets.
The LTC3733CG#TRPBF belongs to Linear's PolyPhase® controller product line, engineered specifically for high-current, multi-phase CPU and GPU core voltage regulation in servers and workstations demanding precision, efficiency, and robust protection.
FAQ
What is the maximum output current supported by the LTC3733CG#TRPBF?
The LTC3733CG#TRPBF itself does not deliver current - it controls external N-channel MOSFETs. In a properly designed 3-phase system with appropriate MOSFETs, inductors, and thermal management, the LTC3733CG#TRPBF enables up to 120 A total output current, as confirmed in the datasheet's "6-Phase, 90A to 120A Operation" feature and Figure 1 application circuit.
Does the LTC3733CG#TRPBF support synchronization to an external clock?
No - the LTC3733CG#TRPBF (G-package SSOP variant) does not support external clock synchronization. Its PLLIN pin is not bonded out; only the LTC3733-1 variant (QFN package) includes PLLIN functionality. The LTC3733CG#TRPBF uses PLLFLTR for DC frequency setting only, with a fixed 210–530 kHz range.
What is the purpose of the FCB pin on the LTC3733CG#TRPBF?
The FCB (Forced Continuous Bias) pin on the LTC3733CG#TRPBF selects operating mode: <0.6 V enables forced continuous PWM; open enables Burst Mode®; tied to VCC enables stage shedding. This single-pin configurability eliminates external mode-selection logic and adapts light-load efficiency strategy to system requirements without firmware changes.
How does the LTC3733CG#TRPBF implement short-circuit protection?
The LTC3733CG#TRPBF uses a dual-stage approach: (1) foldback current limiting activates when VOUT drops below 70% of nominal, reducing peak current; (2) the SS pin capacitor discharges during sustained overcurrent, triggering latch-off after a user-set timeout. Both mechanisms are active simultaneously and can be defeated independently via SS pin current injection or FCB configuration.
Is the LTC3733CG#TRPBF compatible with AMD EPYC™ processors?
No - the LTC3733CG#TRPBF is designed specifically for AMD Opteron™ CPUs using parallel 5-bit VID signaling. AMD EPYC™ processors require SVI2 serial interface and different voltage programming protocols. Using LTC3733CG#TRPBF with EPYC™ would result in incorrect voltage setting and potential system instability.
LTC3733CG#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 36-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Controller, AMD
- Voltage - Input:
- 4V ~ 36V
- Number of Outputs:
- 1
- Voltage - Output:
- 0.8V ~ 1.55V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 36-SSOP
LTC3733CG#TRPBF FAQ
1.How can I place an order for LTC3733CG#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3733CG#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3733CG#TRPBF reliable?
The price and inventory of LTC3733CG#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3733CG#TRPBF is usually 5 days.
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Once your LTC3733CG#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3733CG#TRPBF?
For technical support, including LTC3733CG#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3733CG#TRPBF requirements.
6.How does Aetrix verify that LTC3733CG#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC3733CG#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3733CG#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC3733CG#TRPBF?
All LTC3733CG#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3733CG#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3733CG#TRPBF part is unused and in its original packaging.
Return procedure for LTC3733CG#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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