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Analog Devices Inc. LTC3735EUHF
- Part No.:
- LTC3735EUHF
- Manufacturer:
- Analog Devices Inc.
- Category:
- Special Purpose Regulators
- Package:
- 38-WFQFN Exposed Pad
- Datasheet:
-
LTC3735EUHF.pdf
- Description:
- IC CTRLR DC/DC 2PH HI EFF 38-QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,456
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Product details
Overview
LTC3735EUHF from Analog Devices (formerly Linear Technology) is a 2-phase, synchronous step-down DC/DC controller IC designed for Intel mobile CPU core power delivery. It drives all-N-channel MOSFETs with antiphase operation up to 550kHz, delivers ±1% output voltage accuracy across 0.7V–1.708V via 6-bit IMVP-IV VID interface, and supports resistor-programmable boot-up and deeper sleep voltages - deployed in high-current laptop VRMs and server CPU power stages.
For engineers reviewing the LTC3735EUHF datasheet, LTC3735EUHF pinout, LTC3735EUHF application, or LTC3735EUHF equivalent, this page provides verified technical context on its dual-phase current-mode control, PSIB-selectable power-saving mode, OPTI-LOOP® compensation, stage shedding, and thermal performance with θJA = 34°C/W in the 38-lead QFN package.
Technical Context
The LTC3735EUHF implements a constant-frequency, current-mode architecture where two output phases operate 180° out-of-phase to halve input/output RMS ripple and double apparent switching frequency. Each phase uses cycle-by-cycle current sharing via differential sense inputs (SENSE1±/SENSE2±) and independent top/bottom gate drivers (TG1/BG1/TG2/BG2) with 5A peak drive capability and <90ns transition times.
It integrates an internal 0.6V reference, VID decoder for IMVP-IV compliance, programmable oscillator (210–550kHz via FREQSET), and dual operational amplifier (VOA+/VOA–/OAOUT) enabling lossless voltage positioning and deep-sleep offset programming. Power state selection is controlled by PSIB (forced continuous vs reverse-current prevention) and DPRSLPVR/STP_CPUB (deeper sleep and deep sleep entry).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Topology | 2-phase synchronous buck controller with antiphase operation |
| Output Voltage Range | 0.7V–1.708V via 6-bit VID; resistor-programmable at boot-up and deeper sleep |
| Switching Frequency | 210kHz–550kHz (programmable via FREQSET pin voltage) |
| Current Sensing | Differential, lossless sensing with 59–85mV threshold range and ±0.1% load regulation |
| Thermal Resistance | θJA = 34°C/W (QFN package); junction max = 125°C |
| Protection Features | Overvoltage (±10%), short-circuit latchoff with defeat, foldback current limit, undervoltage RUN/SS reset |
| Operating Temp | –40°C to +85°C ambient |
Pinout & Package
Package: 38-lead (7mm × 5mm) plastic QFN with exposed signal ground pad (Pin 39). Thermal performance optimized for high-power CPU VRM layouts with low-inductance PGND/SW routing and dedicated BOOST/SW capacitor placement.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VFB (Pin 1) | Error amplifier inverting input | Compares feedback voltage to internal 0.6V reference; sets regulation point |
| DPRSLPVR (Pin 2) | Deeper sleep enable input | High = enter deeper sleep; output voltage set by RDPRSLP/RDPSLP parallel resistance |
| FREQSET (Pin 3) | Oscillator frequency control | 0–2.4V input sets switching frequency from 210kHz to 550kHz |
| PSIB (Pin 4) | Power saving mode select | High = full synchronous mode (fast transient); Low = reverse-current prevention + stage shedding |
| VOA+, VOA– (Pins 5,6) | Internal op-amp inputs | Enable lossless voltage positioning and programmable deep-sleep offset |
| OAOUT (Pin 7) | Op-amp output | Drives external resistive network for AVP or deep-sleep offset generation |
| STP_CPUB (Pin 8) | Deep sleep enable input | Low = deep sleep active; output offset set by RDPSLP resistor ratio |
| SGND (Pin 9) | Signal ground reference | Common analog ground for error amp, op-amp, and sense circuitry |
| SENSE1+, SENSE1– (Pins 10,11) | Phase 1 current sense inputs | Differential measurement across RSENSE1; enables cycle-by-cycle current sharing |
| SENSE2+, SENSE2– (Pins 12,13) | Phase 2 current sense inputs | Differential measurement across RSENSE2; matches Phase 1 for balanced sharing |
| RBOOT (Pin 17) | Boot-up voltage set resistor | Resistor to VOA+ defines output voltage during soft-start before VID takes effect |
| VID0–VID5 (Pins 18–23) | IMVP-IV VID command inputs | 6-bit digital interface for dynamic CPU voltage scaling (0.7V–1.708V) |
| TG1, TG2 (Pins 29,33) | Top N-MOS gate drivers | Floating drivers with PVCC-referenced swing; support bootstrap operation up to 32V SW node |
| BG1, BG2 (Pins 24,26) | Bottom N-MOS gate drivers | Ground-referenced 5A peak drivers; turn off when inductor current reverses (PSIB low) |
| PGOOD (Pin 35) | Power-good status output | Open-drain flag masked for 110µs during VID/state transitions to prevent false resets |
| MCH_PG (Pin 36) | Memory controller power-good input | Delays VID activation by 15 clock cycles after assertion to synchronize with platform sequencing |
| Exposed Pad (Pin 39) | Signal ground | Must be soldered to PCB SGND plane; critical for thermal dissipation (θJA = 34°C/W) and noise immunity |
Key Features
| Feature | Design Value |
|---|---|
| Antiphase 2-phase operation | Reduces input/output capacitor RMS ripple by ~30% and improves transient response via doubled apparent switching frequency |
| OPTI-LOOP® compensation | Enables stable loop response across wide range of output capacitance (100µF–2000µF) and ESR (0.5mΩ–10mΩ) |
| Stage shedding under light load | Disables Phase 2 when DPRSLPVR = high and PSIB = low, cutting gate drive and transition losses to boost efficiency at <5A |
| Lossless voltage positioning (AVP) | Uses internal op-amp and external resistors to generate precise I2R droop without sense resistor power loss |
| Programmable deep-sleep offset | STP_CPUB low + RDPSLP resistor sets % drop below VID voltage (e.g., –15% for memory retention) |
| Short-circuit latchoff with defeat | RUN/SS pin accepts >5µA current to override shutdown during sustained overcurrent, enabling system-level fault recovery |
Applications
| Mobile CPU Core VRM | Server CPU Dual-Rail Power |
|---|---|
Use Scenario: High-current (up to 40A) core voltage regulation for Intel Core i-series mobile processors in ultrabooks and 2-in-1 devices. IC Role / Device Role / Timing Role: Primary 2-phase buck controller managing VID-based dynamic voltage scaling, antiphase ripple cancellation, and PSIB-triggered power-saving mode during idle. Use Value: Enables ±1% output accuracy across 0.7V–1.708V while maintaining <100µs transient recovery and >90% efficiency at 20A load. |
Use Scenario: Dual-input, dual-phase CPU power delivery in rack-mounted servers where VIN rails are split (e.g., 12V + 5V) for thermal and layout optimization. IC Role / Device Role / Timing Role: Controller coordinating load sharing between two independent input sources using separate RSENSE networks per phase. Use Value: Achieves balanced current distribution without external current-sharing ICs, reducing BOM count and improving reliability under asymmetric rail conditions. |
| Laptop Platform Deep Sleep | Intel IMVP-IV Compliant Notebook |
Use Scenario: Entry into deeper sleep states (S3/S4) requiring reduced core voltage (e.g., 0.8V) with fast wake-up latency. IC Role / Device Role / Timing Role: Uses DPRSLPVR and RDPRSLP/RDPSLP resistors to set lower output voltage independent of VID, synchronized via MCH_PG timing. Use Value: Cuts CPU leakage power by >40% versus active VID voltage while retaining sub-10ms wake-up time due to pre-biased op-amp loop. |
Use Scenario: Full IMVP-IV compliance in premium notebooks requiring seamless VID transitions, PGOOD masking, and adaptive voltage positioning. IC Role / Device Role / Timing Role: Implements all IMVP-IV mandatory features: 6-bit VID decoding, PGOOD adaptive masking (110µs), STP_CPUB-controlled deep sleep, and MCH_PG-synchronized sequencing. Use Value: Eliminates need for external VID translators or sequencers; reduces design validation time and ensures BIOS compatibility across Intel platforms. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 2-phase synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL95831IRZ | Single-chip solution with integrated MOSFET drivers and PMBus interface; no external op-amp for AVP | Targets newer Intel platforms (IMVP-8/9); lacks resistor-programmable boot/deep-sleep voltage | Choose ISL95831IRZ for digital control and telemetry; LTC3735EUHF remains preferred for analog AVP and legacy IMVP-IV designs |
| TPS51220ARGER | Single-phase controller with integrated LDO bias rail; supports only one phase and no stage shedding | Suitable for low-power CPUs (<15A); cannot replace 2-phase topology or antiphase ripple reduction | Select TPS51220ARGER only for cost-sensitive single-phase applications; LTC3735EUHF required for >20A or ripple-sensitive designs |
Compared with ISL95831IRZ and TPS51220ARGER, the LTC3735EUHF uniquely combines antiphase 2-phase control, analog lossless AVP, and resistor-programmable multi-state voltage settings - making it irreplaceable for validated IMVP-IV mobile CPU VRMs requiring analog flexibility and thermal efficiency at 34°C/W.
Availability
LTC3735EUHF is available at Aetrix Electronics and suitable for mobile CPU VRMs, server motherboard power delivery, and Intel IMVP-IV-compliant notebook designs requiring stable component supply, long-lifecycle support, and traceable sourcing.
Supply support for LTC3735EUHF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, datasheet archives, and application engineering for legacy Linear parts including the LTC3735EUHF.
The LTC3735EUHF belongs to Linear's PolyPhase® controller family, engineered specifically for high-efficiency, multi-phase CPU/GPU core power delivery in space-constrained mobile and server platforms.
FAQ
What is the thermal resistance (θJA) of the LTC3735EUHF?
The LTC3735EUHF has a junction-to-ambient thermal resistance of 34°C/W when mounted on a standard 4-layer PCB with 2oz copper and the exposed pad properly soldered to SGND. This value assumes recommended layout per the datasheet - including thermal vias under the pad and minimal trace length to PGND. The SSOP variant (LTC3735EG) has θJA = 85°C/W.
How does the LTC3735EUHF implement stage shedding?
The LTC3735EUHF implements stage shedding by disabling Phase 2 when both PSIB is low (enabling reverse-current prevention) and DPRSLPVR is high (signaling deeper sleep entry). In this condition, only Phase 1 remains active, eliminating gate drive and switching losses from the second channel - improving light-load efficiency by up to 8% at 3A output current.
Can the LTC3735EUHF operate with different input voltages on each phase?
Yes, the LTC3735EUHF supports dual-input operation: each phase can be powered from a separate VIN rail (e.g., 12V and 5V) by routing PVCC and PGND independently per channel and selecting appropriate RSENSE values. This is enabled by its fully independent current sense and gate drive architecture - confirmed in the Applications Information section of the LTC3735EUHF datasheet.
What is the function of the OAOUT pin on the LTC3735EUHF?
The OAOUT pin on the LTC3735EUHF is the output of the internal operational amplifier, used to generate lossless voltage positioning (AVP) or deep-sleep offset voltages. When configured with external resistors between VOA+, OAOUT, and VOUT, it injects a precise I2R droop signal into the feedback loop - eliminating the need for a power-wasting sense resistor while maintaining tight regulation during load transients.
Does the LTC3735EUHF support Intel IMVP-IV compliance out of the box?
Yes, the LTC3735EUHF natively supports Intel IMVP-IV compliance with built-in 6-bit VID decoding (VID0–VID5), PGOOD adaptive masking (110µs), MCH_PG synchronization (15-cycle delay), STP_CPUB deep sleep control, and DPRSLPVR deeper sleep signaling - all implemented in hardware without firmware or external logic.
LTC3735EUHF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 38-WFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Applications:
- Controller, Intel Mobile CPU
- Voltage - Input:
- -
- Number of Outputs:
- 1
- Voltage - Output:
- 0.7V ~ 1.71V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 38-QFN (5x7)
LTC3735EUHF FAQ
1.How can I place an order for LTC3735EUHF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3735EUHF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3735EUHF reliable?
The price and inventory of LTC3735EUHF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3735EUHF is usually 5 days.
3.What payment methods are accepted for LTC3735EUHF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3735EUHF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3735EUHF?
LTC3735EUHF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3735EUHF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3735EUHF?
For technical support, including LTC3735EUHF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3735EUHF requirements.
6.How does Aetrix verify that LTC3735EUHF is sourced from the original manufacturer or authorized distributors?
All LTC3735EUHF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3735EUHF meets industry standards.
7.What is the process for return or replacement of LTC3735EUHF?
All LTC3735EUHF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3735EUHF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3735EUHF part is unused and in its original packaging.
Return procedure for LTC3735EUHF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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