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Analog Devices Inc. LTC3770EG#PBF

Part No.:
LTC3770EG#PBF
Manufacturer:
Analog Devices Inc.
Category:
DC DC Switching Controllers
Package:
28-SSOP (0.209", 5.30mm Width)
Datasheet:
AetrixLTC3770EG#PBF.pdf
Description:
IC REG CTRLR BUCK 28SSOP
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:2,007

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Product details

Overview

LTC3770EG#PBF from Analog Devices (formerly Linear Technology) is a synchronous step-down switching regulator controller with valley current mode control, output voltage tracking, programmable margining, and PLL-based external clock synchronization. It operates from 4V to 32V input, delivers 0.6V ±0.67% reference accuracy, supports ≤100ns minimum on-time, and enables resistor-programmable switching frequency without a sense resistor. It is used in high-performance server power supplies for ASIC and memory rail regulation.

For engineers reviewing the LTC3770EG#PBF datasheet, LTC3770EG#PBF pinout, LTC3770EG#PBF application, or LTC3770EG#PBF equivalent, key selection criteria include its no-RSENSE current sensing architecture, ±0.67% 0.6V reference tolerance, 28-lead SSOP package thermal performance (θJA = 130°C/W), and dual N-channel MOSFET driver capability with <2.5Ω pull-up/down resistance.

Technical Context

The LTC3770EG#PBF implements constant on-time, valley current mode control using an internal one-shot timer whose on-time (tON) is set by ION pin current and VON pin voltage - enabling stable operation at ultra-low duty cycles down to 2%. Its phase-locked loop accepts external clock inputs via PLLIN and uses PLLFLTR for loop filtering, allowing precise frequency synchronization without jitter accumulation.

Fault protection includes output overvoltage detection (±10% VFB window), input undervoltage lockout (3.2V–4.0V hysteresis), cycle-by-cycle current limit with adjustable foldback, and micropower shutdown (IQ < 30μA). Power sequencing is managed through TRACK/SS pin with 1.4μA internal soft-start current and external capacitor timing.

Key Specifications

ParameterValue and Actual Design Meaning
Input Voltage Range4V to 32V - supports wide-range industrial and server input rails including 5V, 12V, and 24V bus systems.
Reference Voltage Accuracy±0.67% at 0.6V - ensures tight output regulation critical for DDR memory and ASIC core voltages.
Min On-Time≤100ns - enables high VIN-to-low VOUT conversion (e.g., 24V → 0.6V) at practical frequencies without pulse skipping.
Current Sense ArchitectureNo RSENSE option - uses bottom MOSFET RDS(ON) or optional external resistor; VRNG pin sets nominal sense voltage (50–200mV).
Switching Frequency ControlResistor-programmable (ION pin) + PLL sync (PLLIN/PLLFLTR) - allows fixed-frequency design or system-level clock alignment.
Driver Output CapabilityTG/BG drivers with ≤2.5Ω on-resistance - drives high gate-charge N-channel MOSFETs with fast rise/fall times (20ns @ 3300pF).
Protection FeaturesOV/UV lockout, current foldback, PGOOD monitoring, and shutdown IQ < 30μA - meets reliability requirements for unattended server operation.

Pinout & Package

Package: 28-lead plastic SSOP (G package), 5.0mm × 10.2mm body, exposed pad not present (unlike QFN variant), θJA = 130°C/W.

PinCircuit RoleDesign Meaning
RUN (Pin 1)Enable control inputLogic-high (>1.5V) initiates startup; low disables both MOSFETs and reduces IQ to <30μA.
VON (Pin 2)On-time voltage inputSets tON proportionally to VOUT when tied to output; clamped to 0.6V–4.8V internally.
PGOOD (Pin 3)Open-drain status outputPulled low if VFB exits ±10% window after 25μs mask timer - signals valid regulation to system supervisor.
VRNG (Pin 4)Sense range programmingSets nominal current sense threshold (50–200mV); determines max valley current via RSENSE or RDS(ON).
VFB (Pin 5)Error amplifier feedbackCompares output divider voltage against internal 0.6V reference; closed-loop regulation point.
ITH (Pin 6)Error amp output / current thresholdVoltage (0–2.4V) sets valley current comparator threshold; 0.75V = zero-current level.
SGND (Pin 7)Signal ground referenceReturn for all small-signal pins (VFB, ITH, PLLIN); must connect to PGND at single point to avoid noise coupling.
MARGIN1/MARGIN0 (Pins 8–9)Margining state select2-bit logic inputs (with 50kΩ internal pulldowns) configure margin-high/margin-low/no-margin modes for production testing.
ION (Pin 10)Frequency-setting current sourceSinks current proportional to VIN (IION ≈ VIN/RON/3); sets tON and thus operating frequency.
VREFIN (Pin 11)Reference voltage inputAccepts 0.5V–1.0V external reference; overrides internal 0.6V for custom regulation points.
VREFOUT (Pin 12)Buffered 0.6V reference outputProvides low-noise 0.6V reference (≤50μA sink); no >100pF capacitor allowed to preserve stability.
MPGM (Pin 13)Margining current inputResistor-to-ground sets margining offset current; works with VREFOUT–VREFIN resistor to define % margin.
TRACK/SS (Pin 14)Tracking & soft-start nodeInternal 1.4μA current charges external capacitor for controlled VOUT ramp; also accepts master VFB for rail tracking.
PLLFLTR (Pin 15)PLL loop filterConnects external RC network to stabilize PLL; defaults to 1.18V when unsynchronized.
PLLIN (Pin 16)External clock input50kΩ internal termination to SGND; accepts TTL/CMOS clock for frequency locking.
VIN (Pin 17)Main supply inputPrimary power for INTVCC regulator and logic; requires local 0.1–1μF ceramic decoupling to PGND.
ZVIN (Pin 18)Zener-trim voltage inputConnected to INTVCC under normal operation; used in factory trimming of internal references.
Z1/Z2 (Pins 19–20)Zener-trim controlGrounded during normal operation; used in production for post-package calibration and tracking adjustment.
INTVCC (Pin 21)Internal 5V regulator outputSupplies gate drivers and control circuitry; requires ≥4.7μF low-ESR capacitor to PGND.
BG (Pin 22)Bottom gate driver outputDrives bottom N-MOSFET gate between PGND and INTVCC; ≤2.5Ω RDOWN ensures fast turn-off.
PGND (Pin 23)Power ground returnHigh-current return for bottom MOSFET source, CIN(–), and CVCC(–); must be low-inductance PCB connection.
SENSE– (Pin 24)Current sense (–) inputInternally bonded to PGND in SSOP; used only in UH package - omitted function in LTC3770EG#PBF.
SENSE+ (Pin 25)Current sense (+) inputInternally bonded to SW in SSOP; provides Kelvin sensing path when external RSENSE is used.
SW (Pin 26)Switch nodeConnects to drain of top MOSFET and source of bottom MOSFET; swings from ~–0.3V to VIN.
TG (Pin 27)Top gate driver outputDrives top N-MOSFET gate with swing = INTVCC superimposed on SW node; ≤2.5Ω RUP ensures fast turn-on.
BOOST (Pin 28)Bootstrap supplyConnects to (+) terminal of bootstrap capacitor; floats up to VIN + INTVCC during top-FET conduction.

Key Features

FeatureDesign Value
No-RSENSE valley current sensingEliminates sense resistor losses and BOM cost while maintaining accurate current limiting using MOSFET RDS(ON).
Programmable output voltage marginingTwo-pin digital control (MARGIN0/MARGIN1) enables ±5% or ±10% VOUT deviation for production test without hardware change.
Output voltage trackingTRACK/SS pin supports master-slave sequencing across multiple rails (e.g., VDDQ/VDDIO) with matched slew rates.
PLL-based external clock synchronizationEnables deterministic switching timing across multiple converters to reduce EMI peak amplitude and simplify filtering.
Adjustable cycle-by-cycle current limitVRNG pin and ITH voltage jointly define peak/valley current thresholds - supports dynamic load transient response tuning.
Micropower shutdown with PGOOD monitoringIQ < 30μA in shutdown + open-drain PGOOD output enable reliable power sequencing and fault reporting in multi-rail systems.

Applications

Server Core Voltage RegulationASIC Power Sequencing

Use Scenario: Regulating 0.8V–1.2V core supplies for high-end CPUs and FPGAs in rack-mounted servers with strict ripple and transient requirements.

IC Role / Device Role / Timing Role: Primary synchronous buck controller managing high-current (up to 60A) POL conversion with tracking and margining support.

Use Value: ±0.67% reference accuracy and ≤100ns min on-time ensure stable low-VOUT operation at 24V input; VRNG pin enables precise current limit setting without sense resistor loss.

Use Scenario: Coordinating startup/shutdown order of multiple voltage rails (e.g., VCCINT, VCCAUX, VCCO) in Xilinx or Intel FPGA systems.

IC Role / Device Role / Timing Role: Master controller using TRACK/SS pin to drive slave regulators, enforcing defined voltage ramp timing and hold-off delays.

Use Value: Internal 1.4μA soft-start current and external capacitor allow programmable ramp rate; PGOOD output feeds into FPGA configuration logic for safe initialization.

DDR Memory SupplyIndustrial High-VIN DC/DC

Use Scenario: Generating tightly regulated 1.2V or 1.35V VDDQ for DDR4/LPDDR4 memory modules in telecom base stations and storage controllers.

IC Role / Device Role / Timing Role: Synchronous buck controller with margining capability for production test validation of memory interface voltage margins.

Use Value: MARGIN0/MARGIN1 pins enable automated ±5% voltage deviation during burn-in testing; ±10% PGOOD window ensures robust fault detection during memory stress tests.

Use Scenario: Converting 24V or 32V industrial bus voltage to 3.3V or 5V for PLC I/O modules and sensor interfaces requiring high input transient immunity.

IC Role / Device Role / Timing Role: Wide-input buck controller with UVLO (3.2V–4.0V) and OV protection, supporting unregulated front-end supplies.

Use Value: 4V–32V input range and 32V absolute max rating tolerate automotive-style load dump transients; INTVCC LDO ensures stable gate drive even during brownout.

Equivalent & Alternatives

The following parts are listed as comparable options for similar synchronous buck controller applications.

Alternative PartTechnical DifferenceApplication DifferenceSelection Advice
LTC3891EG#PBFIncludes integrated 5V bias supply for gate drivers; lacks margining and PLL sync; wider 4.5V–60V input range.Preferred for simpler designs where margining and clock sync are unnecessary and higher VIN is required.Select when system does not require voltage margining or external clock synchronization but needs extended input voltage range and self-contained bias supply.
MP2918GL-ZMonolithic 30V buck converter (integrated MOSFETs); no TRACK/SS or margining; lower quiescent current (15μA).Suitable for space-constrained, medium-power applications (<20A) where board area and BOM count are prioritized over flexibility.Choose for compact, cost-sensitive designs needing integrated power stage - not for high-current, multi-rail, or test-margining use cases.

Compared with LTC3770EG#PBF, LTC3891EG#PBF offers higher VIN tolerance and integrated bias but sacrifices margining and PLL sync; MP2918GL-Z reduces component count via integration but eliminates programmable features and high-current scalability essential for server and ASIC applications.

Availability

LTC3770EG#PBF is available at Aetrix Electronics and suitable for server power supply design, ASIC voltage regulation, and DDR memory rail generation requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.

Supply support for LTC3770EG#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for the LTC portfolio.

The LTC3770EG#PBF belongs to Linear's high-performance power controller family, designed specifically for demanding server, data center, and high-speed digital system power delivery where precision regulation, sequencing, and testability are mandatory.

FAQ

What is the minimum on-time specification for the LTC3770EG#PBF, and why does it matter?

The LTC3770EG#PBF has a guaranteed minimum on-time of ≤100ns. This enables stable operation at very low duty cycles - for example, stepping down 24V input to 0.6V output (2.5% duty cycle) without pulse-skipping or regulation loss. The short tON(MIN) is critical for high-VIN, low-VOUT applications like CPU core supplies and ensures predictable frequency behavior across line and load variations.

Can the LTC3770EG#PBF operate without an external current sense resistor?

Yes, the LTC3770EG#PBF supports no-RSENSE operation by using the bottom MOSFET's RDS(ON) as the current sensing element. In the SSOP package (LTC3770EG#PBF), SENSE+ is internally bonded to SW and SENSE– to PGND, eliminating need for external sense components. VRNG pin sets nominal sense voltage (50–200mV), and ITH voltage defines the valley current threshold - enabling efficient, low-loss current limiting.

How does the TRACK/SS pin function in both soft-start and voltage tracking modes?

The TRACK/SS pin serves dual roles: during startup, an internal 1.4μA current charges an external capacitor to generate a controlled VOUT ramp (soft-start); in tracking mode, it accepts a scaled version of a master regulator's VFB signal to force identical voltage ramp profiles across multiple rails. For LTC3770EG#PBF, this enables precise sequencing of DDR VDDQ/VDDIO or FPGA core/I/O supplies without additional ICs.

What are the key differences between the LTC3770EG#PBF (SSOP) and LTC3770EUH#PBF (QFN) packages?

The LTC3770EG#PBF uses a 28-lead SSOP package (θJA = 130°C/W) with SENSE+/SENSE– pins internally bonded to SW/PGND - optimized for no-RSENSE designs. The LTC3770EUH#PBF uses a 32-lead 5mm × 5mm QFN (θJA = 34°C/W) with separate SENSE+ and SENSE– pins for Kelvin sensing with external resistors. Both share identical electrical functionality, but thermal performance and current sensing flexibility differ significantly.

Does the LTC3770EG#PBF support forced continuous conduction mode (FCCM) at light loads?

Yes, the LTC3770EG#PBF supports FCCM via the FCB pin. When FCB is pulled below 0.6V (e.g., tied to SGND), the controller forces continuous conduction mode regardless of load - eliminating audible noise and output voltage ripple associated with discontinuous mode. This is especially valuable in sensitive analog or RF subsystems powered from the same supply rail as the LTC3770EG#PBF.

LTC3770EG#PBF Specifications

Product attributes
Attribute value
Manufacturer:
Analog Devices Inc.
Series:
-
Package/Case:
28-SSOP (0.209", 5.30mm Width)
Packaging:
Tube
Product Status:
Active
Output Type:
Transistor Driver
Function:
Step-Down
Output Configuration:
Positive
Topology:
Buck
Number of Outputs:
1
Output Phases:
1
Voltage - Supply (Vcc/Vdd):
4V ~ 32V
Frequency - Switching:
-
Duty Cycle (Max):
90%
Synchronous Rectifier:
Yes
Clock Sync:
No
Serial Interfaces:
-
Control Features:
Current Limit, Enable, On Time Control, Power Good, Soft Start, Tracking
Operating Temperature:
-40°C ~ 85°C (TA)
Grade:
-
Qualification:
-
Mounting Type:
Surface Mount
Supplier Device Package:
28-SSOP

LTC3770EG#PBF FAQ

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The price and inventory of LTC3770EG#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3770EG#PBF is usually 5 days.

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Once your LTC3770EG#PBF order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LTC3770EG#PBF?

For technical support, including LTC3770EG#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3770EG#PBF requirements.

6.How does Aetrix verify that LTC3770EG#PBF is sourced from the original manufacturer or authorized distributors?

All LTC3770EG#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3770EG#PBF meets industry standards.

7.What is the process for return or replacement of LTC3770EG#PBF?

All LTC3770EG#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3770EG#PBF, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LTC3770EG#PBF part is unused and in its original packaging.

Return procedure for LTC3770EG#PBF:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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