My Inquiry
My Account
Analog Devices Inc. LTC3770EG#TRPBF
- Part No.:
- LTC3770EG#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 28-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
LTC3770EG#TRPBF.pdf
- Description:
- IC REG CTRLR BUCK 28SSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,278
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3770EG#TRPBF from Analog Devices (formerly Linear Technology) is a synchronous step-down switching regulator controller with valley current mode control, output voltage tracking, programmable margining, and PLL-based external clock synchronization. It operates from 4V to 32V input, delivers 0.6V to ≤32V output (via duty cycle), achieves ≤100ns minimum on-time, and supports up to 90% duty cycle at 200kHz - enabling high-efficiency power delivery for server CPU core rails and ASIC supply domains.
For engineers reviewing the LTC3770EG#TRPBF datasheet, LTC3770EG#TRPBF pinout, LTC3770EG#TRPBF application, or LTC3770EG#TRPBF equivalent, key selection criteria include its resistor-programmable switching frequency, no-RSENSE current sensing capability using MOSFET RDS(ON), ±0.67% reference accuracy, and dual N-channel gate driver with <2.5Ω pull-up/down resistance - all critical for high-density, high-accuracy DC/DC designs in compute infrastructure.
Technical Context
The LTC3770EG#TRPBF implements constant-on-time, valley current mode control without requiring an external sense resistor - instead using SENSE+/SENSE– inputs to measure either a discrete shunt or bottom MOSFET VDS. Its internal 5V INTVCC regulator powers dual N-channel drivers (TG/BG), while the ITH pin serves as both error amplifier output and current comparator threshold control point.
Phase-locked loop synchronization via PLLIN enables deterministic timing alignment across multiple converters; VRNG pin sets nominal current sense threshold (50mV–200mV); TRACK/SS pin supports master-slave output voltage tracking and soft-start ramp control; MARGIN0/MARGIN1 pins enable three-state voltage margining (high/low/none) for production test validation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4V to 32V - supports wide-range industrial and server front-end supplies without pre-regulation. |
| Reference Voltage Accuracy | ±0.67% at 0.6V - ensures tight output regulation for sub-1V ASIC cores and memory rails. |
| Min On-Time | ≤100ns - enables high VIN-to-low VOUT conversion (e.g., 24V→1.2V @ 5% duty) without pulse-skipping. |
| Duty Cycle Range | 2% to 90% at 200kHz - accommodates both high-step-down and high-step-up (buck-boost derived) configurations. |
| Current Sense Threshold | Adjustable 50mV–308mV via VRNG pin - allows precise current limit setting with MOSFET RDS(ON) or shunt resistors. |
| Driver Output Resistance | TG: ≤2.5Ω pull-up / ≤2.5Ω pull-down; BG: ≤3Ω pull-up / ≤1.5Ω pull-down - drives large gate charges with fast rise/fall times (20ns into 3300pF). |
| Shutdown Current | <30μA - enables ultra-low-power system standby states without auxiliary LDOs. |
Pinout & Package
Package: 28-Lead Plastic SSOP (G package), 5.0mm × 10.2mm body, exposed pad not present. Thermal resistance θJA = 130°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RUN (Pin 1) | Enable control input | Logic-high ≥1.5V enables operation; <1.5V forces shutdown with <30μA quiescent current. |
| VON (Pin 2) | On-time voltage input | Sets tON proportionally to VOUT; clamped to 0.6V–4.8V internally for stable frequency vs. output variation. |
| PGOOD (Pin 3) | Open-drain power-good monitor | Pulls low when VFB deviates >±10% from regulation point after 25μs mask timer - enables system-level fault sequencing. |
| VRNG (Pin 4) | Sense range programming input | Sets nominal current sense threshold (50mV–200mV) - determines overcurrent trip point and foldback behavior. |
| VFB (Pin 5) | Error amplifier feedback input | Compares output divider voltage against internal 0.6V reference; gain set by external compensation network on ITH pin. |
| ITH (Pin 6) | Error amp output / current threshold | 0.75V = zero-current threshold; 0–2.4V range adjusts valley current limit - used for loop compensation and current limiting. |
| SGND (Pin 7) | Signal ground reference | Return for all small-signal circuitry (VFB, ITH, PLLFLTR); must connect to PGND at single point to avoid noise coupling. |
| MARGIN1 (Pin 8) | Margining MSB control | With MARGIN0, selects margin high/low/none state; internal 50kΩ pull-down enables default no-margin operation. |
| MARGIN0 (Pin 9) | Margining LSB control | Paired with MARGIN1 to configure ±3% or ±5% output margin for production test and burn-in. |
| ION (Pin 10) | Frequency-setting current source | Sinks current proportional to VIN/RON; sets tON and thus operating frequency - enables VIN-compensated constant-frequency operation. |
| VREFIN (Pin 11) | Reference input voltage | Accepts 0.5V–1.0V external reference to override internal 0.6V; enables precision tracking of another rail or custom voltage setpoint. |
| VREFOUT (Pin 12) | Buffered 0.6V reference output | Provides low-impedance 0.6V source for remote sensing or slave rail tracking; max sink current 50μA. |
| MPGM (Pin 13) | Margining current input | Sets margin offset voltage via resistor to ground; works with VREFOUT–VREFIN resistor to define margin magnitude. |
| TRACK/SS (Pin 14) | Tracking & soft-start node | Internal 1.4μA current charges external capacitor for soft-start; when used as slave, accepts master VFB for synchronized ramp-up. |
| PLLFLTR (Pin 15) | PLL loop filter connection | Connects external RC filter to stabilize phase-locked loop; defaults to 1.18V when unsynchronized - indicates PLL lock status. |
| PLLIN (Pin 16) | External clock sync input | 50kΩ internal termination to SGND; accepts TTL/CMOS clock for deterministic switching edge alignment across multiple phases. |
| VIN (Pin 17) | Main power input | Supplies internal circuits and bootstrap recharge path; requires local 0.1–1μF ceramic decoupling to PGND. |
| ZVIN (Pin 18) | Zener-trim voltage reference | Must connect to INTVCC; provides stable bias for internal trimming circuits during production calibration. |
| Z1 (Pin 19) | Zener-trim control | Ground during normal soft-start; tie to INTVCC to disable soft-start current during tracking mode. |
| Z2 (Pin 20) | Zener-trim control | Ground or tie to INTVCC for normal operation; used internally for post-package parameter adjustment. |
| INTVCC (Pin 21) | Internal 5V regulator output | Supplies gate drivers and analog circuitry; requires ≥4.7μF low-ESR capacitor to PGND for stability and transient response. |
| BG (Pin 22) | Bottom gate driver output | Drives bottom N-MOSFET gate between PGND and INTVCC; capable of 4A peak, 50mA RMS current. |
| PGND (Pin 23) | Power ground return | High-current return for bottom MOSFET source, CIN(–), and CVCC(–); must be low-inductance connection to minimize switching noise. |
| SW (Pin 24) | Switch node | Connects to inductor, top MOSFET drain, and SENSE+ (in no-RSENSE mode); swings from ~–0.7V to VIN. |
| TG (Pin 25) | Top gate driver output | Drives top N-MOSFET gate with swing equal to INTVCC superimposed on SW node voltage - requires bootstrap capacitor (CB). |
| BOOST (Pin 26) | Bootstrap supply input | Connects to (+) terminal of CB; floats up to VIN + INTVCC during top switch conduction - enables high-side N-MOSFET drive. |
| Z0 (Pin 27) | Dead time control | DC voltage input adjusts dead time between TG-off and BG-on transitions - prevents shoot-through in high-frequency operation. |
| FCB (Pin 28) | Forced continuous mode | Ground to force CCM at light load; tie to INTVCC to enable DCM; use resistive divider for secondary-winding sync in fly-buck topologies. |
Key Features
| Feature | Design Value |
|---|---|
| No-RSENSE current sensing | Uses bottom MOSFET RDS(ON) as current sense element - eliminates shunt resistor losses and board space, improving efficiency by ~0.5–1.2% at full load. |
| Programmable voltage margining | Three-state digital control (MARGIN0/MARGIN1) enables ±3% or ±5% output deviation for production test - reduces need for external margining DACs or relays. |
| Output voltage tracking | TRACK/SS pin accepts master rail's VFB to replicate ramp profile - ensures controlled power-up/power-down sequencing between core and I/O rails in multi-rail systems. |
| PLL-based clock synchronization | PLLIN input locks switching edges to external system clock - eliminates beat frequencies and EMI peaks in multi-phase or multi-rail systems. |
| Adjustable cycle-by-cycle current limit | VRNG and ITH pins jointly define real-time current threshold - enables precise short-circuit protection and foldback limiting without additional ICs. |
Applications
| Server CPU Core Supply | ASIC Power Delivery |
|---|---|
Use Scenario: Regulating 0.8V–1.2V at up to 100A for high-performance x86 or ARM processors in rack-mounted servers. IC Role / Device Role / Timing Role: Primary synchronous buck controller managing top/bottom N-MOSFETs, implementing dynamic voltage scaling and telemetry via ITH/VFB monitoring. Use Value: ≤100ns min on-time enables 48V→1V conversion at 500kHz; ±0.67% reference ensures <±6mV regulation error across temperature - meeting Intel VR13/VR14 spec margins. | Use Scenario: Powering FPGA or ASIC core logic with tight transient response requirements (<50mV droop under 50A/μs load step). IC Role / Device Role / Timing Role: Valley current mode controller with programmable soft-start and tracking - synchronizes with I/O rail for coordinated power sequencing. Use Value: 20ns driver rise/fall times and <2.5Ω gate drive impedance reduce switching transition losses; TRACK/SS pin enables <100ns inter-rail skew during power-up. |
| Memory Subsystem Rail | Industrial PLC Power Module |
Use Scenario: Generating DDR4/DDR5 VDDQ (1.2V/1.1V) and VPP (2.5V) rails with margining support for production binning and lifetime testing. IC Role / Device Role / Timing Role: Dual-rail controller configured in master-slave tracking mode - one LTC3770EG#TRPBF controls VDDQ, second tracks VPP with matched slew rate. Use Value: MARGIN0/MARGIN1 pins allow automated ±5% voltage stress testing without firmware changes; VRNG pin enables consistent current limit across temperature for reliable short-circuit protection. | Use Scenario: High-reliability 24V input to 3.3V/5V/12V isolated or non-isolated outputs in programmable logic controllers with extended temperature operation. IC Role / Device Role / Timing Role: Main buck controller supporting wide VIN (4V–32V), undervoltage lockout (3.2V), and robust fault handling (OVP/UVP/current foldback). Use Value: –40°C to +85°C guaranteed operation; 32V absolute max input withstands industrial transients; PGOOD output interfaces directly to PLC watchdog circuitry. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ISL8113IRZ-T7A | Fixed 5V INTVCC; no VRNG pin; uses external current sense resistor only; no margining pins. | Lacks voltage margining and MOSFET RDS(ON)-based sensing - requires shunt resistor and external margin DAC for test coverage. | Select when cost-sensitive designs prioritize simplicity over margining and no-RSENSE flexibility. |
| MP2940AGQSE-Z | Integrated MOSFET drivers with adaptive dead time; supports PMBus interface; no PLL sync or TRACK/SS pin. | Offers digital telemetry but lacks analog tracking and external clock sync - unsuitable for deterministic multi-phase timing alignment. | Select when system-level telemetry and thermal management outweigh need for analog rail coordination. |
Compared with ISL8113IRZ-T7A and MP2940AGQSE-Z, the LTC3770EG#TRPBF uniquely combines no-RSENSE sensing, hardware-based voltage margining, and PLL synchronization - making it optimal for high-accuracy, high-density server and ASIC power where analog control integrity and testability are critical.
Availability
LTC3770EG#TRPBF is available at Aetrix Electronics and suitable for server power supply design, ASIC core rail generation, and industrial embedded power modules requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC3770EG#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for the LTC portfolio.
The LTC3770EG#TRPBF belongs to Linear's high-performance power controller family, designed specifically for high-efficiency, high-accuracy DC/DC conversion in datacenter, telecom, and industrial computing applications where precision regulation and robust fault handling are mandatory.
FAQ
What is the minimum on-time specification for the LTC3770EG#TRPBF, and why does it matter?
The LTC3770EG#TRPBF has a guaranteed minimum on-time of ≤100ns. This enables high input-to-output voltage step-down ratios (e.g., 24V→1.0V at 4.2% duty cycle) without pulse-skipping or audible noise - critical for modern server and ASIC supplies where high VIN and low VOUT coexist. The spec is measured at ION = –180μA and VON = 0V per the datasheet's Electrical Characteristics table.
Can the LTC3770EG#TRPBF operate without an external current sense resistor?
Yes. The LTC3770EG#TRPBF supports no-RSENSE operation by using the bottom N-MOSFET's RDS(ON) as the current sense element. Connect SENSE+ to SW and SENSE– to PGND. The VRNG pin sets the effective sense threshold (50mV–200mV), and the current comparator monitors valley current via the MOSFET's VDS drop - eliminating shunt losses and PCB area.
How does the TRACK/SS pin function in master-slave voltage tracking configurations?
In master-slave mode, the TRACK/SS pin of the slave LTC3770EG#TRPBF accepts the master's VFB signal through a resistor divider. The internal 1.4μA current source is disabled, allowing the slave to replicate the master's soft-start ramp and regulation point - ensuring monotonic, skew-controlled power-up across multiple rails like CPU core and I/O in server motherboards.
What is the purpose of the VRNG pin on the LTC3770EG#TRPBF, and how is it configured?
The VRNG pin on the LTC3770EG#TRPBF sets the nominal current sense threshold (50mV–200mV) used for overcurrent protection and current-mode control. It is configured via a resistive divider from INTVCC (0.5V–2V). Tying VRNG to SGND or INTVCC defaults to 50mV or 200mV respectively. The actual sense threshold is ~0.133×VRNG, enabling precise current limit tuning without changing external components.
Does the LTC3770EG#TRPBF support external clock synchronization, and how is it implemented?
Yes. The LTC3770EG#TRPBF supports external clock synchronization via the PLLIN pin. An external TTL/CMOS clock applied to PLLIN locks the internal phase-locked loop, aligning switching edges to the system clock. The PLLFLTR pin connects to an external RC filter to stabilize loop dynamics. This eliminates beat frequencies and reduces EMI in multi-phase or multi-rail systems - confirmed in the Functional Diagram and Applications Information sections.
LTC3770EG#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 28-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 1
- Output Phases:
- 1
- Voltage - Supply (Vcc/Vdd):
- 4V ~ 32V
- Frequency - Switching:
- -
- Duty Cycle (Max):
- 90%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, On Time Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-SSOP
LTC3770EG#TRPBF FAQ
1.How can I place an order for LTC3770EG#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3770EG#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3770EG#TRPBF reliable?
The price and inventory of LTC3770EG#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3770EG#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC3770EG#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3770EG#TRPBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3770EG#TRPBF?
LTC3770EG#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3770EG#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3770EG#TRPBF?
For technical support, including LTC3770EG#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3770EG#TRPBF requirements.
6.How does Aetrix verify that LTC3770EG#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC3770EG#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3770EG#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC3770EG#TRPBF?
All LTC3770EG#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3770EG#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3770EG#TRPBF part is unused and in its original packaging.
Return procedure for LTC3770EG#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3770EG#TRPBF Tags
-
UCC28C45DR
Texas Instruments
-
UCC28C40DR
Texas Instruments
-
UCC28C43DR
Texas Instruments
-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments
-
MIC2102YML-TR
Microchip Technology
-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments
-
LM5155DSSR
Texas Instruments
-
LM25085MYX/NOPB
Texas Instruments
-
UCC2813DTR-0
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
