Analog Devices Inc. LTC3773EUHF#TRPBF
- Part No.:
- LTC3773EUHF#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 38-WFQFN Exposed Pad
- Datasheet:
-
LTC3773EUHF#TRPBF.pdf
- Description:
- IC REG CTRLR BUCK 38QFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,385
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Product details
Overview
LTC3773EUHF#TRPBF from Analog Devices (formerly Linear Technology) is a high-performance, 3-phase, triple-output synchronous step-down DC/DC controller with programmable up/down voltage tracking. It supports input voltages from 3.3V to 36V, delivers ±1% 0.6V feedback reference accuracy over temperature, operates at up to 700kHz per phase with 120° phase separation, and integrates onboard MOSFET drivers for external N-channel FETs. It is used in multi-rail server power supplies requiring precise rail sequencing and high efficiency.
For engineers reviewing the LTC3773EUHF#TRPBF datasheet, LTC3773EUHF#TRPBF pinout, LTC3773EUHF#TRPBF application, or LTC3773EUHF#TRPBF equivalent, key selection criteria include its triple-output current-mode architecture, 38-pin 5mm × 7mm QFN package with exposed PGND pad, selectable Burst Mode®/Discontinuous/Continuous light-load operation, OPTI-LOOP® compensation, and phase-lockable 160–700kHz switching frequency.
Technical Context
The LTC3773EUHF#TRPBF implements a constant-frequency, current-mode control architecture across three independent channels, each with dedicated ITH, VFB, SENSE+, SENSE−, TRACK, and SDB pins. Its error amplifier features 2.7 mmho transconductance and 3 MHz gain-bandwidth, enabling stable loop response with minimal output capacitance via OPTI-LOOP® compensation.
Phase relationships are configurable via PHASEMD pin (120°/90°/270° offsets), and synchronization is supported through PLLIN/FC input (160–700kHz range) with PLLFLTR filter pin. Fault protection includes output overvoltage detection (±7% PGOOD trip threshold), input undervoltage lockout (4.1V nominal), and current foldback under short-circuit conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 3.3V to 36V - supports wide-input industrial and telecom power rails without pre-regulation |
| Feedback Reference | 0.6V ±1% over –40°C to 85°C - enables accurate regulation of outputs from 0.6V to 5V |
| Switching Frequency | 160kHz to 700kHz - adjustable via PLLFLTR voltage or external sync; reduces RMS input current via 120° interleaving |
| Current Sense Threshold | 65mV to 90mV - sets peak current limit with high accuracy; supports low-value RSENSE for minimal power loss |
| Thermal Resistance θJA | 34°C/W - achieved via 38-pin QFN with exposed PGND pad; enables high-power density designs up to 15A per channel |
| Light-Load Modes | Burst Mode®, Discontinuous, or Forced Continuous - selectable via PLLIN/FC pin to optimize efficiency vs. ripple trade-off |
| Tracking Accuracy | ±0.5% tracking error during startup/shutdown - ensures controlled power-up/down sequencing across three independent rails |
Pinout & Package
Package: 38-lead (5mm × 7mm) plastic QFN with exposed thermal pad (Pin 39 = PGND). Requires soldering of exposed pad to PCB ground plane for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BOOST1–3 | Top gate bootstrap supply | Provides floating bias for high-side N-MOSFET drivers; swings up to VIN + VDR |
| TG1–3 | Top gate drive output | Drives gate of external high-side N-MOSFETs with rail-to-rail swing referenced to SWx node |
| BG1–3 | Bottom gate drive output | Drives gate of external low-side N-MOSFETs; referenced to PGND |
| SW1–3 | Switching node | Connects to source of high-side FET and drain of low-side FET; high dv/dt node requiring careful layout |
| SENSE1+ / SENSE1− SENSE2+ / SENSE2− SENSE3+ / SENSE3− |
Differential current sense inputs | Measure voltage across external RSENSE to set per-channel current limit; reject common-mode noise |
| VFB1–3 | Error amplifier feedback input | Compares output voltage divider signal to 0.6V internal reference; determines regulation setpoint |
| ITH1–3 | Error amplifier output / compensation node | Controls peak inductor current; connects to RC network for OPTI-LOOP® stability compensation |
| TRACK1–3 | Tracking input | Enables sequential, coincident, or ratiometric startup/shutdown of multiple outputs; 1μA pull-up current |
| SDB1–3 | Channel shutdown enable | Active-low per-channel enable with distinct thresholds (1.2V/1.8V/2.4V); supports staggered power-up |
| PGOOD | Open-drain power-good indicator | Asserts low if any output deviates >±7% from target for >100μs; used for system sequencing and fault reporting |
| PLLIN/FC | Sync input / mode select | Accepts external clock (160–700kHz) or selects Burst/Discontinuous/Continuous mode via DC voltage level |
| PHASEMD | Phase configuration | Selects 120° (float), 90°/270° (VCC), or 60°/180° (GND) inter-channel phase offset and CLKOUT alignment |
| VCC | Main logic supply | 4.5V–6V input powering internal circuitry; requires local 1μF bypass to SGND |
| VDR | Driver supply | Supplies gate drivers and charges bootstrap capacitors; must be decoupled tightly to PGND |
| SGND | Signal ground | Separate analog ground reference for feedback and compensation; routed directly to PGND under IC |
| PGND | Power ground | Return path for all driver currents and bottom FET sources; connected to exposed QFN pad |
Key Features
| Feature | Design Value |
|---|---|
| Triple 3-phase synchronous control | Three independent current-mode controllers with 120° phase shift reduce input capacitor RMS current by ~58% vs. single-phase |
| Programmable up/down tracking | Supports sequential, coincident, or ratiometric startup/shutdown across three outputs using resistor dividers and external caps on TRACK pins |
| OPTI-LOOP® compensation | Minimizes required output capacitance by optimizing loop bandwidth and phase margin without external type-II/type-III networks |
| Selectably optimized light-load efficiency | Burst Mode® extends battery life in standby; Discontinuous mode maintains constant frequency while avoiding reverse inductor current |
| Robust fault protection | Includes overvoltage (PGOOD), undervoltage lockout (4.1V VCC reset), and current foldback-no external circuitry needed for basic protection |
| Flexible synchronization & phase control | PLLIN/FC accepts external clocks up to 700kHz; PHASEMD pin configures inter-channel timing for EMI reduction and thermal balancing |
Applications
| Server Multi-Rail Power | Telecom Base Station PSU |
|---|---|
|
Use Scenario: Generating 2.5V/15A, 1.8V/15A, and 1.2V/15A rails from a 12V intermediate bus in a 1U server motherboard. IC Role / Device Role / Timing Role: Triple-output 3-phase controller managing rail sequencing, dynamic load transient response, and thermal distribution across three phases. Use Value: 120° interleaving cuts input ripple current by >50%, reducing bulk capacitor count and board area; tracking ensures safe FPGA core/voltage I/O power-up order. |
Use Scenario: Providing isolated, sequenced 3.3V, 2.5V, and 1.2V supplies for RF transceiver ASICs and baseband processors in macrocell BTS units. IC Role / Device Role / Timing Role: High-accuracy current-mode controller delivering tight load regulation (<±1%) and fast transient recovery (<10μs) under bursty traffic loads. Use Value: ±1% VFB accuracy and 0.6V reference ensure stable core voltage under temperature variation; PGOOD monitoring enables system-level fault isolation. |
| FPGA Power Delivery | Industrial PLC CPU Supply |
|
Use Scenario: Powering Xilinx Kintex Ultrascale+ FPGA banks requiring simultaneous 1.2V core, 0.85V AUX, and 1.8V I/O rails with strict ramp-rate control. IC Role / Device Role / Timing Role: Tracking-capable triple controller coordinating soft-start timing across rails using external RC networks on TRACK1–3 pins. Use Value: Programmable tracking thresholds (1.2V/1.8V/2.4V on SDB pins) and linear ramp on TRACK pins prevent FPGA configuration errors due to out-of-spec voltage sequencing. |
Use Scenario: Delivering robust 5V, 3.3V, and 2.5V supplies for ARM Cortex-A9-based PLC controllers operating in harsh 0°C–70°C ambient environments. IC Role / Device Role / Timing Role: Industrial-grade controller with –40°C to 85°C rating, integrated UVLO, and current foldback protecting against motor-drive-induced bus transients. Use Value: 34°C/W θJA enables full 15A/channel operation without forced air; fault flags (PGOOD, OCP) interface directly with PLC watchdog logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar triple-output synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2940AGQ-DC | Single-chip 3-phase controller with integrated MOSFETs (40V max VIN); no external TRACK/SDB pin flexibility; fixed 500kHz frequency | Lower BOM count but limited to ≤12A/channel; unsuitable for >36V inputs or custom tracking profiles | Choose MP2940AGQ-DC only when board space is critical and input voltage stays below 40V with fixed 500kHz operation. |
| LTC3873EUFD#PBF | Dual-output version (not triple); identical 38-pin QFN package and pin-compatible on shared signals; lacks TRACK2/TRACK3 and SDB2/SDB3 pins | Cannot support three independently tracked rails; requires second controller for third output | Choose LTC3873EUFD#PBF only when only two regulated rails are needed and footprint compatibility with LTC3773EUHF#TRPBF is prioritized. |
Compared with MP2940AGQ-DC and LTC3873EUFD#PBF, the LTC3773EUHF#TRPBF uniquely provides three fully independent, trackable outputs with 36V input capability, external MOSFET flexibility, and user-configurable phase alignment-making it the sole option for high-reliability, multi-rail telecom and server applications demanding design margin and long-term supply continuity.
Availability
LTC3773EUHF#TRPBF is available at Aetrix Electronics and suitable for server power supplies, telecom base station PSUs, and industrial PLC CPU supplies requiring stable component supply, long lifecycle support, and guaranteed traceable sourcing.
Supply support for LTC3773EUHF#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for all Linear-branded power management ICs.
The LTC3773EUHF#TRPBF belongs to Linear's high-performance multi-phase controller family, designed specifically for high-efficiency, low-noise, and tightly sequenced power delivery in datacenter, networking, and industrial computing systems.
FAQ
What is the maximum input voltage supported by the LTC3773EUHF#TRPBF?
The LTC3773EUHF#TRPBF supports a maximum input voltage of 36V, with absolute maximum ratings specifying SWn pins up to 36V and BOOSTn pins up to 42V. Operation above 36V violates the recommended operating conditions and risks damage or degraded performance. The controller is optimized for 3.3V–36V input ranges typical in intermediate bus architectures for servers and telecom equipment.
How does the LTC3773EUHF#TRPBF implement power-up tracking across three outputs?
The LTC3773EUHF#TRPBF uses dedicated TRACK1, TRACK2, and TRACK3 pins to enable sequential, coincident, or ratiometric voltage ramping. During startup, the error amplifier compares VFB to the rising voltage on the TRACK pin (instead of the 0.6V reference), allowing smooth, controlled output rise. External RC networks on these pins set ramp rates, and resistor dividers from one output can drive another TRACK pin to enforce tracking relationships-fully supported in the LTC3773EUHF#TRPBF's pinout and internal logic.
Can the LTC3773EUHF#TRPBF operate with only one or two outputs enabled?
Yes, the LTC3773EUHF#TRPBF supports per-channel shutdown via individual SDB1, SDB2, and SDB3 pins. Driving any SDBx pin below 0.4V disables that channel's gate drivers and associated control loop while maintaining functionality of the remaining channels. This allows flexible configuration-for example, using only Channel 1 for 2.5V and disabling Channels 2 and 3-without hardware modification or firmware changes.
What thermal performance can be expected from the LTC3773EUHF#TRPBF in a standard 4-layer PCB layout?
In a standard 4-layer PCB with 2oz copper, 1-in² thermal pad connected to internal ground planes, and no forced airflow, the LTC3773EUHF#TRPBF achieves a junction-to-ambient thermal resistance (θJA) of 34°C/W. At full 15A per channel with 12V input and 2.5V output, total power dissipation is ~3.2W, resulting in ~115°C junction rise above ambient-well within the 125°C maximum rating when ambient is ≤65°C. Layout best practices (via stitching under exposed pad, short thick traces for PGND/VDR) are essential to maintain this performance.
Does the LTC3773EUHF#TRPBF support synchronization to an external clock source?
Yes, the LTC3773EUHF#TRPBF supports external clock synchronization via the PLLIN/FC pin, which accepts input frequencies from 160kHz to 700kHz. When driven by an external oscillator, the internal phase-locked loop locks the switching frequency and phase of all three channels to the input clock, enabling deterministic EMI reduction and coordinated operation with other power stages. The PLLFLTR pin sets loop bandwidth and must be configured with an RC network per the datasheet.
LTC3773EUHF#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 38-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 3
- Output Phases:
- 3
- Voltage - Supply (Vcc/Vdd):
- 3.3V ~ 36V
- Frequency - Switching:
- 220kHz ~ 560kHz
- Duty Cycle (Max):
- 98.5%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Enable, Power Good, Tracking
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 38-QFN (5x7)
LTC3773EUHF#TRPBF FAQ
1.How can I place an order for LTC3773EUHF#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3773EUHF#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3773EUHF#TRPBF reliable?
The price and inventory of LTC3773EUHF#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3773EUHF#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC3773EUHF#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3773EUHF#TRPBF transactions.
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4.How is shipping managed for LTC3773EUHF#TRPBF?
LTC3773EUHF#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3773EUHF#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3773EUHF#TRPBF?
For technical support, including LTC3773EUHF#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3773EUHF#TRPBF requirements.
6.How does Aetrix verify that LTC3773EUHF#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC3773EUHF#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3773EUHF#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC3773EUHF#TRPBF?
All LTC3773EUHF#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3773EUHF#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3773EUHF#TRPBF part is unused and in its original packaging.
Return procedure for LTC3773EUHF#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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