Analog Devices Inc. LTC3828EUH#PBF
- Part No.:
- LTC3828EUH#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LTC3828EUH#PBF.pdf
- Description:
- IC REG CTRLR BUCK 32QFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,439
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Product details
Overview
LTC3828EUH#PBF from Analog Devices (formerly Linear Technology) is a dual, 2-phase synchronous step-down controller driving all-N-channel MOSFET stages for high-efficiency DC/DC conversion. It delivers ±1% output voltage accuracy, phase-lockable 260–550 kHz operation, and precision tracking across two independent outputs - used in telecom infrastructure power supplies requiring tight voltage coordination between ASIC core and I/O rails.
For engineers reviewing the LTC3828EUH#PBF datasheet, LTC3828EUH#PBF pinout, LTC3828EUH#PBF application, or LTC3828EUH#PBF equivalent, key selection criteria include its dual 180°-phased architecture, OPTI-LOOP® compensation for wide-output-capacitance compatibility, TRCKSS pin-based soft-start/tracking, FCB/PLLIN mode selection (Burst/Continuous/Skip), and 5mm × 5mm QFN-32 package with exposed thermal pad.
Technical Context
The LTC3828EUH#PBF implements constant-frequency current-mode control with two independent 180°-interleaved channels, each featuring a transconductance error amplifier (gm = 1.3 mmho, GBW = 3 MHz) and precision 0.8 V reference (±1% over temperature). Its dual-phase architecture reduces input RMS current by ~27% versus single-phase dual controllers, lowering EMI and input capacitor stress.
Phase synchronization is achieved via FCB/PLLIN pin (accepting external clock or DC voltage 0–2.4 V for PLL frequency tuning) and PLLFLTR pin (sourcing/sinking ±17 μA), enabling daisy-chained multi-phase systems up to 6-phase using CLKOUT. The PHSMD pin (QFN-only) selects relative phase alignment: 0°/180°/240° for Controller 2 and 60°/90°/120° for CLKOUT.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 28 V (30 V absolute max); supports 12 V telecom, 24 V industrial, and multi-cell Li-ion battery inputs. |
| Output Voltage Accuracy | ±1% over –40°C to +85°C; enables stable 2.5 V/3.3 V/5 V rails for FPGA, ASIC, and DSP core logic without post-regulation. |
| Switching Frequency Range | 260 kHz to 550 kHz (phase-lockable); adjustable via PLLFLTR voltage (0–2.4 V DC) or external clock on FCB/PLLIN. |
| Current Sense Threshold | 62–88 mV (adjustable via ITH voltage); provides accurate cycle-by-cycle current limiting with foldback during short-circuit. |
| Soft-Start Current | 0.5–1.2 μA on TRCKSS pins; sets controlled ramp rate for both outputs during startup and tracking sequences. |
| Power Good Threshold | ±7.5% of set output voltage on either VOSENSE pin; open-drain PGOOD asserts low if either channel deviates beyond tolerance. |
| Duty Cycle Max | 99.4% dropout operation; sustains regulation down to VIN ≈ VOUT, critical for high-input-voltage, low-output-voltage applications. |
Pinout & Package
Package: 32-lead (5 mm × 5 mm) plastic QFN with exposed thermal pad (Pin 33 = SGND, must be soldered to PCB). Thermal resistance θJA = 34°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOSENSE1 / VOSENSE2 (Pins 1, 13) | Error amplifier feedback input | Accepts remote-sensed voltage divider output; enables precise regulation independent of PCB trace IR drop. |
| TRCKSS1 / TRCKSS2 (Pins 7, 29) | Soft-start & tracking control | Internal 1.2 μA current source charges external capacitor; master/slave tracking achieved by replicating VOSENSE1 voltage on TRCKSS2. |
| FCB/PLLIN (Pin 5) | Mode select & sync input | Selects Burst Mode (0.85–4.3 V), forced continuous (0–0.75 V), or constant frequency (>4.8 V); also accepts external clock for PLL lock. |
| PHSMD (Pin 4) | Phase selector (QFN only) | Sets relative phase between controllers and CLKOUT: GND = 0°/180°/60°, OPEN = 0°/180°/90°, INTVCC = 0°/240°/120°. |
| TG1/TG2 (Pins 16, 25) & BG1/BG2 (Pins 18, 19) | N-MOSFET gate drivers | TG drives top-side floating N-FETs (INTVCC-referenced swing); BG drives bottom-side synchronous N-FETs (0–5 V swing). |
| CLKOUT (Pin 28) | Phase-synchronized clock output | Provides 90°-shifted clock (vs Channel 1) to synchronize additional LTC3828 or compatible controllers in multi-phase systems. |
| PGOOD (Pin 27) | Open-drain status indicator | Pulls low if either enabled channel's VOSENSE deviates >±7.5%; ignores shutdown channels - supports independent rail monitoring. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 180° interleaved phases | Reduces input RMS current by ~27%, cuts input capacitor size/cost, and lowers conducted EMI vs single-phase dual controllers. |
| OPTI-LOOP® compensation | Enables stable loop response across wide range of ceramic output capacitors (4.7 μF–56 μF) and ESR values without external compensation redesign. |
| Tracking with coincident/ratiometric modes | TRCKSS pins support both simultaneous ramp-up (coincident) and proportional ramp (ratiometric) for multi-rail sequencing in ASIC/FPGA power domains. |
| Three light-load operating modes | Burst Mode (high efficiency <10% load), skip-cycle (low noise), and forced continuous (PWM, reverse-current capable) - selected via FCB/PLLIN voltage. |
| Output overvoltage protection | Dedicated comparator disables TG and enables BG if VOSENSE exceeds +7.5%, preventing damage to downstream logic during transients or feedback fault. |
| Thermal-enhanced QFN package | 32-pin 5 mm × 5 mm QFN with exposed pad (θJA = 34°C/W) enables high-power density designs up to 5 A per channel at 85°C ambient. |
Applications
| Telecom Base Station Power | ASIC/FPGA Core & I/O Supply |
|---|---|
Use Scenario: Dual-rail power for RF transceiver ASICs requiring 1.2 V core and 2.5 V I/O with strict sequencing and ripple limits. IC Role / Device Role / Timing Role: Dual-phase controller providing interleaved 1.2 V/2.5 V outputs with ratiometric tracking and PGOOD monitoring per rail. Use Value: Reduces input capacitor RMS current by 27%, enabling smaller 1206 MLCCs and cutting board area by 35% vs discrete controllers. | Use Scenario: High-current, low-noise supply for Xilinx Kintex-7 FPGA with separate 1.0 V core and 2.5 V auxiliary rails. IC Role / Device Role / Timing Role: Synchronous buck controller delivering 5 A per rail with ±1% accuracy, soft-start coordination, and independent RUN pin enable/disable. Use Value: OPTI-LOOP® ensures stability with low-ESR polymer caps; CLKOUT synchronizes third-phase controller for 15 A total core current. |
| Industrial PLC CPU Module | Automotive ADAS Domain Controller |
Use Scenario: 3.3 V and 5 V power for ARM Cortex-A53 CPU and CAN/LIN interface ICs in harsh-temperature PLC modules. IC Role / Device Role / Timing Role: Dual-channel controller with –40°C to +85°C rating, UVLO at 4 V, and robust current foldback for field-induced shorts. Use Value: 99.4% duty cycle maintains regulation during brownout; PGOOD signals microcontroller reset if either rail fails. | Use Scenario: Power management for NVIDIA Orin-based ADAS domain controller requiring 1.8 V GPU, 1.2 V CPU, and 3.3 V sensor interface rails. IC Role / Device Role / Timing Role: Master-slave tracking configuration where 1.2 V CPU rail controls 1.8 V GPU ramp via TRCKSS; FCB/PLLIN set to Burst Mode for idle efficiency. Use Value: Dual-phase architecture suppresses 500 kHz switching noise near radar receivers; exposed pad improves thermal margin under 40 W dissipation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3855IUHF#PBF | Single-channel, 60 V max input, no tracking or CLKOUT; supports higher VIN but lacks dual-phase coordination. | Best for single-rail, high-input-voltage industrial converters - not suitable for dual-rail tracking or multi-phase sync. | Select LTC3828EUH#PBF when dual 180°-phased outputs, TRCKSS-based sequencing, or CLKOUT daisy-chaining are required. |
| MP8770GQ-Z | Monolithic dual-phase controller (integrated MOSFETs), 16 V max VIN, fixed 500 kHz, no PLL sync or PHSMD pin. | Targeted at space-constrained consumer applications; cannot replace LTC3828EUH#PBF in high-VIN (>16 V), thermally demanding, or externally synchronized systems. | Choose LTC3828EUH#PBF for design flexibility: external FET selection, wide VIN, thermal optimization, and deterministic phase alignment. |
Compared with LTC3855IUHF#PBF and MP8770GQ-Z, the LTC3828EUH#PBF uniquely combines dual-phase interleaving, precision voltage tracking, PLL-enabled multi-controller synchronization, and 28 V input capability - making it the only option for high-reliability telecom and industrial dual-rail systems requiring coordinated startup and thermal headroom.
Availability
LTC3828EUH#PBF is available at Aetrix Electronics and suitable for telecom infrastructure, ASIC power supply, and industrial equipment applications requiring stable component supply, long-term lifecycle support, and guaranteed RoHS-compliant lead-free packaging.
Supply support for LTC3828EUH#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for the LTC portfolio.
The LTC3828 belongs to Linear's high-performance power controller family designed for efficiency-critical, multi-rail DC/DC conversion in telecom, computing, and industrial systems - emphasizing precision regulation, thermal robustness, and flexible sequencing.
FAQ
What is the maximum input voltage rating for the LTC3828EUH#PBF?
The LTC3828EUH#PBF has an absolute maximum input voltage (VIN) rating of 30 V, with recommended continuous operation from 4.5 V to 28 V. Exceeding 30 V risks permanent damage per Absolute Maximum Ratings. This 28 V operational ceiling supports 24 V industrial buses and multi-cell Li-ion battery inputs while maintaining safety margin.
How does the TRCKSS pin enable voltage tracking between the two outputs of the LTC3828EUH#PBF?
The LTC3828EUH#PBF uses internal 1.2 μA current sources on TRCKSS1 and TRCKSS2 to charge external capacitors. In master-slave mode, the VOSENSE1 feedback voltage is replicated via resistor divider onto TRCKSS2, causing Channel 2's error amplifier to servo its output to match Channel 1's ramp profile - enabling precise ratiometric or coincident tracking without external ICs.
Can the LTC3828EUH#PBF operate in forced continuous conduction mode (FCCM), and how is it configured?
Yes, the LTC3828EUH#PBF enters forced continuous conduction mode when the FCB/PLLIN pin voltage is held below 0.75 V (e.g., tied to ground). In this mode, both top and bottom MOSFETs switch continuously regardless of load, allowing bidirectional current flow - useful for applications requiring zero-output-ripple or reverse-current capability, though at reduced light-load efficiency.
What thermal performance can be expected from the LTC3828EUH#PBF in its QFN-32 package?
The LTC3828EUH#PBF in the 5 mm × 5 mm QFN package has a junction-to-ambient thermal resistance (θJA) of 34°C/W when the exposed pad (Pin 33) is properly soldered to a 4-layer PCB with ≥2 in² copper pour. At 85°C ambient and 2 W dissipation, junction temperature remains at ~153°C - within the 125°C absolute max limit only with adequate layout; derating is required above 1.5 W continuous.
Does the LTC3828EUH#PBF support synchronization to an external clock, and what is the required signal format?
Yes, the LTC3828EUH#PBF supports external clock synchronization via the FCB/PLLIN pin. It accepts TTL- or CMOS-level square waves from 260 kHz to 550 kHz. Upon detection, Channel 1 locks to the external clock's rising edge; Channel 2 automatically follows with 180° phase offset. No external components are needed beyond standard AC-coupling if DC bias differs from INTVCC.
LTC3828EUH#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 28V
- Frequency - Switching:
- 260kHz ~ 550kHz
- Duty Cycle (Max):
- 99.4%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Enable, Phase Control, Power Good, Tracking
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-QFN (5x5)
LTC3828EUH#PBF FAQ
1.How can I place an order for LTC3828EUH#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3828EUH#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3828EUH#PBF reliable?
The price and inventory of LTC3828EUH#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3828EUH#PBF is usually 5 days.
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Once your LTC3828EUH#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3828EUH#PBF?
For technical support, including LTC3828EUH#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3828EUH#PBF requirements.
6.How does Aetrix verify that LTC3828EUH#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3828EUH#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3828EUH#PBF meets industry standards.
7.What is the process for return or replacement of LTC3828EUH#PBF?
All LTC3828EUH#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3828EUH#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3828EUH#PBF part is unused and in its original packaging.
Return procedure for LTC3828EUH#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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