Analog Devices Inc. LTC3838EFE#TRPBF
- Part No.:
- LTC3838EFE#TRPBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
LTC3838EFE#TRPBF.pdf
- Description:
- IC REG CTRLR BUCK 38TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3838EFE#TRPBF from Analog Devices (formerly Linear Technology) is a dual-channel, PolyPhase® synchronous step-down DC/DC controller driving all-N-channel MOSFETs. It delivers ±0.67% output voltage accuracy on Channel 1 via differential sensing, supports 4.5V–38V input and 0.6V–5.5V output ranges, and enables fast transient response with controlled-on-time valley current mode control - used in high-density point-of-load converters for computing and datacom systems.
For engineers reviewing the LTC3838EFE#TRPBF datasheet, LTC3838EFE#TRPBF pinout, LTC3838EFE#TRPBF application, or LTC3838EFE#TRPBF equivalent, key selection criteria include differential remote-sense capability (±500mV ground offset tolerance), 30ns minimum on-time, 200kHz–2MHz programmable frequency, DTR-based overshoot suppression, and dual independent or PolyPhase operation modes.
Technical Context
The LTC3838EFE#TRPBF implements valley current mode control with controlled-on-time architecture, enabling constant-frequency steady-state operation independent of VIN, VOUT, and load. Its differential sensing loop on Channel 1 uses internal 0.6V reference and rejects up to ±500mV common-mode ground shift between local and remote output grounds.
Channel 2 operates either as an independent ±1% regulator or synchronizes with Channel 1 in PolyPhase configuration (180° or 240° phase shift selectable via PHASMD). The device integrates dual gate drivers (TG/BG), internal 5.3V DRVCC1 regulator, EXTVCC switchover, and detect-transient (DTR) logic that disables BG during rapid load release to minimize overshoot.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V to 38V - supports wide-input industrial and telecom power rails without pre-regulation. |
| Output Voltage Accuracy (Ch1) | ±0.67% over temperature with differential sensing - ensures stable core voltage regulation despite PCB ground bounce. |
| Min On/Off Time | tON(MIN) = 30ns, tOFF(MIN) = 90ns - enables high VIN-to-low VOUT conversion (e.g., 36V→0.6V) at high frequency without pulse skipping. |
| Switching Frequency | 200kHz to 2MHz (RT-programmable) - allows optimization of size (high f) vs. efficiency (low f) in space-constrained designs. |
| Current Sensing | RSENSE or DCR sensing with 30mV/60mV/100mV selectable max threshold - supports low-loss inductor sensing or precision shunt-based current limiting. |
| Thermal Performance | TJMAX = 125°C, θJA = 28°C/W (TSSOP) - enables reliable operation in convection-cooled embedded systems without forced airflow. |
| Protection Features | Overvoltage (±7.5%), undervoltage, current limit foldback, short-circuit recovery, and thermal shutdown - reduces need for external fault management circuitry. |
Pinout & Package
Package: 38-lead plastic TSSOP (FE package), 12.5mm × 6.1mm × 1.1mm, exposed PGND pad (Pin 39) requiring solder connection to PCB thermal plane.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VOUTSENSE1+, VOUTSENSE1– | Differential feedback inputs (Ch1) | Enable remote sensing across PCB ground shifts up to ±500mV - critical for accurate CPU/GPU core rail regulation. |
| SENSE1+, SENSE1– / SENSE2+, SENSE2– | Valley current sense inputs | Support Kelvin-connected RSENSE or DCR networks; SENSE– pins include 500kΩ internal resistor to SGND for bias stability. |
| DTR1, DTR2 | Load-release transient detection | Internal 2.5µA pull-up; falling below INTVCC/2 triggers BG disable to clamp inductor current decay and suppress VOUT overshoot. |
| PHASMD | Phase mode select | SGND = 180° phase shift (standard PolyPhase), FLOAT = 180° + 90° CLKOUT, INTVCC = 240° + 120° CLKOUT - enables multi-phase interleaving for ripple cancellation. |
| TRACK/SS1, TRACK/SS2 | Soft-start & tracking control | 1µA internal pull-up; capacitor to ground sets ramp time; external voltage source enables power sequencing with other rails. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent or PolyPhase operation | Single IC supports two isolated outputs or one high-current output with interleaved phases - reduces input/output capacitance and EMI. |
| Differential remote sensing (Ch1) | Rejects up to ±500mV ground potential difference between controller and load - eliminates regulation error from high-current PCB trace IR drop. |
| Controlled-on-time valley current mode | Delivers fast load-step response (<5µs settling) while maintaining constant switching frequency - simplifies EMI filter design vs. variable-frequency architectures. |
| Programmable current sense range | VRNG1/VRNG2 pins set max sense voltage to 30mV/60mV/100mV - optimizes signal-to-noise ratio for diverse current-sense element choices (shunt or DCR). |
| Integrated gate drivers & bias regulators | DRVCC1 (5.3V) and EXTVCC switchover eliminate need for external LDOs; TG/BG drivers support >10A peak gate charge delivery per channel. |
Applications
| Server VRM | Telecom Intermediate Bus |
|---|---|
Use Scenario: Regulating 1.2V/15A CPU core voltage from 12V intermediate bus in dual-processor server motherboard. IC Role / Device Role / Timing Role: Dual-channel controller operating in independent mode: Ch1 supplies CPU VDD, Ch2 supplies memory I/O rail with tracking soft-start. Use Value: Differential sensing maintains ±0.67% accuracy despite >300mV ground shift between VRM and CPU socket; DTR reduces 15A→0A load dump overshoot to <40mV. | Use Scenario: Generating 3.3V/20A and 5V/15A outputs from 48V telecom rectified bus in distributed power architecture. IC Role / Device Role / Timing Role: Configured in PolyPhase mode with 180° phase shift to deliver single 3.3V/35A output using two parallel phases. Use Value: Interleaved operation cuts input RMS current by ~30%, reducing bulk capacitor stress and EMI filter size; 2MHz capability shrinks magnetics volume by 4× vs. 500kHz. |
| Industrial PLC I/O Module | Network Switch ASIC Supply |
Use Scenario: Providing isolated 1.8V/8A and 3.3V/6A rails for FPGA and transceivers in harsh-environment programmable logic controller. IC Role / Device Role / Timing Role: Independent dual-channel operation with separate RUN pins enabling staggered power-up and fault isolation. Use Value: Wide 4.5V–38V input range accommodates unregulated 24V DC field wiring; –40°C to 125°C junction rating ensures reliability in sealed enclosures. | Use Scenario: Powering 0.85V/40A ASIC core in 1U network switch with strict ripple and transient requirements. IC Role / Device Role / Timing Role: Two LTC3838EFE#TRPBFs configured in 4-phase PolyPhase (2×2) with synchronized CLKOUT for master-slave timing alignment. Use Value: 30ns tON(MIN) enables direct 12V→0.85V conversion at 1MHz, avoiding inefficient two-stage designs; PGOOD outputs feed FPGA power-good sequencer. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3838-1EFE#TRPBF | Both channels offer ±0.67%/±0.75% differential regulation; single-pin VRNG control; improved current limit accuracy. | Required where Channel 2 also demands high-accuracy remote sensing (e.g., GPU memory rail matching CPU core). | Select when dual differential sensing is mandatory and tighter current limit tolerance (±3%) is needed over standard LTC3838. |
| MP2918GL-Z | Monolithic dual buck (integrated MOSFETs); lower current rating (12A/channel); no differential sensing; fixed 500kHz fSW. | Suitable for cost-sensitive, lower-power applications where layout area is constrained and ±1% accuracy suffices. | Choose for simplified BOM and layout when integrated FETs and reduced feature set (no DTR, no VRNG scaling) are acceptable trade-offs. |
Compared with LTC3838-1EFE#TRPBF, the LTC3838EFE#TRPBF trades dual-differential sensing for greater flexibility in mixed-accuracy applications; versus MP2918GL-Z, it provides higher performance (30ns tON, DTR, programmable fSW) at the cost of external MOSFETs and more complex layout.
Availability
LTC3838EFE#TRPBF is available at Aetrix Electronics and suitable for server VRMs, telecom intermediate bus converters, and industrial PLC power supplies requiring stable component supply, long-term lifecycle support, and guaranteed parametric compliance across –40°C to 125°C.
Supply support for LTC3838EFE#TRPBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance analog and power management portfolio with rigorous automotive- and industrial-grade qualification.
The LTC3838EFE#TRPBF belongs to Linear's PolyPhase® controller family, designed specifically for high-efficiency, high-current DC/DC conversion in computing, datacom, and industrial systems where precision regulation, fast transient response, and thermal robustness are critical.
FAQ
What is the maximum allowable ground potential difference between VOUTSENSE1+ and VOUTSENSE1– for accurate regulation in LTC3838EFE#TRPBF?
The LTC3838EFE#TRPBF supports up to ±500mV common-mode ground offset between VOUTSENSE1+ and VOUTSENSE1– while maintaining ±0.67% output voltage accuracy. This is achieved through its dedicated differential amplifier topology and precision 0.6V internal reference. The specification is validated across –40°C to 125°C junction temperature and applies only to Channel 1; Channel 2 uses single-ended sensing referenced to SGND.
Does LTC3838EFE#TRPBF support synchronization to an external clock, and what are the valid input levels on MODE/PLLIN?
Yes, LTC3838EFE#TRPBF supports external clock synchronization via the MODE/PLLIN pin. Valid input levels are VH ≥ 2V and VL ≤ 0.5V, with input resistance of 600kΩ to SGND. When an external clock is applied, both channels operate in forced continuous mode and lock to the input frequency within ±30% of the RT-programmed nominal frequency. The PHASMD pin determines CLKOUT and channel phase alignment relative to the synchronized clock.
How does the DTR (Detect Transient) feature reduce output voltage overshoot in LTC3838EFE#TRPBF during rapid load release?
The DTR feature in LTC3838EFE#TRPBF monitors load transients by sensing voltage drop on the DTR1/DTR2 pins. When load current drops rapidly, the pin voltage falls below INTVCC/2, triggering immediate bottom gate (BG) turn-off. This allows inductor current to decay faster through freewheeling paths, preventing energy buildup that causes VOUT overshoot. Test data shows >50% reduction in 15A→0A load dump overshoot compared to DTR-disabled operation.
Can LTC3838EFE#TRPBF operate with only one channel enabled, and what is the quiescent current in that state?
Yes, LTC3838EFE#TRPBF supports single-channel operation by pulling either RUN1 or RUN2 low. With only one channel enabled, typical input supply current is 2mA (max 3mA) at 25°C. Shutdown current (both RUN pins low) is 15µA max. The disabled channel's gate drivers, error amplifiers, and current sense circuitry are fully powered down, minimizing system standby loss - critical for always-on subsystems in networking equipment.
What are the thermal limitations and PCB layout requirements for the exposed pad on LTC3838EFE#TRPBF's TSSOP package?
The exposed pad (Pin 39) of the LTC3838EFE#TRPBF TSSOP package is electrically and thermally connected to PGND. It must be soldered to a minimum 200mm² copper thermal pad on the PCB using ≥4 thermal vias (0.3mm diameter) to inner ground planes. Thermal impedance is θJA = 28°C/W under JEDEC JESD51-7 conditions. Failure to properly connect the pad risks exceeding TJMAX = 125°C at full load, triggering thermal shutdown and compromising long-term reliability.
LTC3838EFE#TRPBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 38V
- Frequency - Switching:
- 200kHz ~ 2MHz
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Enable, Frequency Control, Phase Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 38-TSSOP-EP
LTC3838EFE#TRPBF FAQ
1.How can I place an order for LTC3838EFE#TRPBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3838EFE#TRPBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3838EFE#TRPBF reliable?
The price and inventory of LTC3838EFE#TRPBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3838EFE#TRPBF is usually 5 days.
3.What payment methods are accepted for LTC3838EFE#TRPBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3838EFE#TRPBF transactions.
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4.How is shipping managed for LTC3838EFE#TRPBF?
LTC3838EFE#TRPBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3838EFE#TRPBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3838EFE#TRPBF?
For technical support, including LTC3838EFE#TRPBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3838EFE#TRPBF requirements.
6.How does Aetrix verify that LTC3838EFE#TRPBF is sourced from the original manufacturer or authorized distributors?
All LTC3838EFE#TRPBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3838EFE#TRPBF meets industry standards.
7.What is the process for return or replacement of LTC3838EFE#TRPBF?
All LTC3838EFE#TRPBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3838EFE#TRPBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3838EFE#TRPBF part is unused and in its original packaging.
Return procedure for LTC3838EFE#TRPBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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