Analog Devices Inc. LTC3838EUHF#PBF
- Part No.:
- LTC3838EUHF#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 38-WFQFN Exposed Pad
- Datasheet:
-
LTC3838EUHF#PBF.pdf
- Description:
- IC REG CTRLR BUCK 38QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3838EUHF#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, PolyPhase® synchronous step-down DC/DC controller driving all-N-channel MOSFETs. It delivers ±0.67% output voltage accuracy on Channel 1 via differential sensing, supports 4.5V–38V input and 0.6V–5.5V output ranges, and enables fast transient response with controlled-on-time valley current mode control - used in high-density point-of-load converters for computing and datacom systems.
For engineers reviewing the LTC3838EUHF#PBF datasheet, LTC3838EUHF#PBF pinout, LTC3838EUHF#PBF application, or LTC3838EUHF#PBF equivalent, this page provides verified package mapping (38-pin 5mm × 7mm QFN), confirmed pin functions including DTR-based overshoot reduction, differential VOUTSENSE inputs, and validated alternative part selection for dual-phase buck controller designs.
Technical Context
The LTC3838EUHF#PBF implements valley current mode control with controlled-on-time architecture, enabling constant-frequency operation independent of VIN, VOUT, and load. Its dual-channel design supports independent regulation (±0.67% on Ch1, ±1% on Ch2) or interleaved PolyPhase operation with programmable phase offsets (0°/180°/240°) via PHASMD pin.
It integrates differential remote-sense amplifiers for Channel 1 (tolerating ±500mV ground offset), selectable current sense range (30mV/60mV/100mV) per channel via VRNG pins, and load-release transient detection (DTR) to suppress overshoot during rapid load drops - critical for low-voltage, high-current CPU/GPU rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V to 38V - supports wide-input industrial and telecom power rails without pre-regulation. |
| Output Voltage Accuracy (Ch1) | ±0.67% over temperature with differential sensing - ensures stable core voltage under PCB ground bounce up to ±500mV. |
| Switching Frequency Range | 200kHz to 2MHz (RT-programmable) - enables optimization of size vs. efficiency in space-constrained designs. |
| Min. On/Off Time | tON(MIN) = 30ns, tOFF(MIN) = 90ns - supports ultra-low duty cycles (e.g., 0.6V out from 38V in) and near-100% duty cycle for high-VIN, low-VOUT conversion. |
| Current Sense Options | RSENSE or inductor DCR sensing - eliminates need for dedicated sense resistors, reducing power loss and BOM cost. |
| Thermal Package | 38-pin (5mm × 7mm) QFN with exposed PGND pad - θJA = 34°C/W enables >15A per channel operation with standard PCB copper. |
| Protection Features | Overvoltage (±7.5%), undervoltage, current limit foldback, and thermal shutdown - ensures robust operation under fault conditions. |
Pinout & Package
Package: 38-lead plastic QFN (5mm × 7mm), exposed PGND pad (Pin 39), rated for –40°C to +125°C junction temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SENSE1+, SENSE1– | Differential current sense inputs (Ch1) | Support Kelvin RSENSE or DCR sensing; SENSE1– has internal 500kΩ to SGND for bias stability. |
| VOUTSENSE1+, VOUTSENSE1– | Differential output voltage sense (Ch1) | Enables remote sensing with ±500mV common-mode ground offset tolerance - critical for accurate low-VOUT regulation. |
| DTR1, DTR2 | Load-release transient detection inputs | When pulled below 0.5×INTVCC, disables BG to accelerate inductor current decay and reduce VOUT overshoot. |
| PHASMD | Phase mode selector | Configures Ch2 relative phase: SGND = 180°, floating = 180°, INTVCC = 240° - enables optimal ripple cancellation in PolyPhase layouts. |
| MODE/PLLIN | Mode control or external clock sync input | Selects forced continuous/discontinuous mode or synchronizes both channels to external clock within ±30% frequency tolerance. |
Key Features
| Feature | Design Value |
|---|---|
| Differential output sensing (Ch1) | ±0.67% regulation accuracy maintained despite ±500mV remote ground deviation - eliminates ground loop errors in multi-layer PCBs. |
| Controlled-on-time valley current mode | Fast transient response with constant switching frequency across line/load - simplifies EMI filtering and avoids subharmonic oscillation. |
| Programmable current sense range (VRNG1/2) | Three precision ranges (30/60/100mV) set via analog voltage - improves current limit accuracy and noise immunity vs. fixed-threshold comparators. |
| Track/SS inputs with 1µA pull-up | Enables soft-start ramp or precise voltage tracking between multiple rails using external voltage sources - essential for FPGA/CPU sequencing. |
| Integrated gate drivers (TG/BG) | Low RDS(ON) (1.2Ω–2.5Ω) drivers support high-side/lower-side N-MOSFETs directly - reduces external component count and layout complexity. |
Applications
| Server VR13 Core Regulator | AI Accelerator Power Rail |
|---|---|
Use Scenario: Supplies 0.6V–1.2V core voltage to high-performance CPUs with dynamic load steps up to 15A/µs. IC Role / Device Role / Timing Role: Dual-channel PolyPhase controller managing two parallel buck stages with 180° phase shift to halve input/output ripple. Use Value: Differential sensing maintains ±0.67% accuracy despite PCB ground bounce; DTR feature limits overshoot to <30mV during 15A→0A transients. |
Use Scenario: Powers GPU or AI ASIC requiring tightly regulated 0.8V/20A rail with strict sequencing relative to I/O and memory supplies. IC Role / Device Role / Timing Role: Independent Channel 2 regulates auxiliary rail while Channel 1 handles core; TRACK/SS2 enables precise voltage ramp alignment with host controller. Use Value: 30ns minimum on-time supports 0.8V output from 12V input; RSENSE/DCR flexibility allows optimal trade-off between sensing loss and noise immunity. |
| Telecom Baseband Processor | Industrial FPGA Power System |
Use Scenario: Delivers 1.5V/15A to baseband SoC in 48V intermediate bus architecture with wide ambient temperature range. IC Role / Device Role / Timing Role: Operates in forced continuous mode (MODE/PLLIN tied to INTVCC) for predictable ripple and EMI profile across –40°C to +85°C. Use Value: 4.5V–38V input range accommodates 48V-to-12V intermediate bus; ±1% Channel 2 accuracy meets SoC I/O supply tolerance. |
Use Scenario: Powers Xilinx/Intel FPGA with multiple voltage domains (core, AUX, I/O), requiring coordinated startup and fault isolation. IC Role / Device Role / Timing Role: Uses independent RUN1/RUN2 pins to enable/disable rails sequentially; PGOOD1/PGOOD2 feed system supervisor for health monitoring. Use Value: Dual open-drain PGOOD outputs simplify system-level power sequencing; thermal QFN package sustains full load at 85°C ambient with minimal heatsinking. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LTC3838-1 | Both channels offer ±0.67%/±0.75% differential regulation; single-pin VRNG control (30mV/60mV); improved current limit accuracy. | Better suited for dual-rail systems requiring matched accuracy (e.g., DDR memory VDD/VTT), not ideal when one rail needs higher tolerance. | Select LTC3838-1 only if both rails demand sub-1% differential accuracy and simplified current sense configuration is preferred. |
| MP2918GL-Z | Monolithic dual buck (integrated MOSFETs); lower max input (28V); no differential sensing; fixed 500kHz–1.2MHz frequency. | Targets cost-sensitive, medium-power apps (<12A/rail); lacks remote sensing and PolyPhase capability - unsuitable for high-accuracy, high-current rails. | Choose MP2918GL-Z for compact, low-BOM-count designs where input <28V and ±2% accuracy suffices; avoid for server/AI applications requiring LTC3838EUHF#PBF's precision and flexibility. |
Compared with LTC3838-1 and MP2918GL-Z, the LTC3838EUHF#PBF uniquely balances high-accuracy differential sensing on Channel 1, flexible per-channel current sense programming, and full PolyPhase configurability - making it the only option among the three qualified for demanding CPU/GPU core rail designs with ground-isolated loads.
Availability
LTC3838EUHF#PBF is available at Aetrix Electronics and suitable for distributed power systems, point-of-load converters, and computing systems requiring stable component supply with guaranteed long-term availability and traceable sourcing.
Supply support for LTC3838EUHF#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017, inheriting its legacy of high-performance power management ICs with emphasis on precision, efficiency, and reliability.
The LTC3838EUHF#PBF belongs to Linear's PolyPhase® controller product line, designed specifically for high-current, low-voltage DC/DC conversion in servers, networking equipment, and AI hardware where accuracy, transient response, and thermal performance are critical.
FAQ
What is the maximum supported input voltage for the LTC3838EUHF#PBF?
The LTC3838EUHF#PBF supports an absolute maximum input voltage of 40V on the VIN pin, with recommended operating range from 4.5V to 38V. Exceeding 40V risks permanent damage per Absolute Maximum Ratings. The controller maintains stable regulation across this full range when paired with appropriately rated external MOSFETs and passive components.
Does the LTC3838EUHF#PBF support differential sensing on both channels?
No - only Channel 1 (pins VOUTSENSE1+ and VOUTSENSE1–) supports true differential output voltage sensing with ±500mV common-mode ground tolerance. Channel 2 uses single-ended feedback referenced to SGND (via VFB2), delivering ±1% accuracy. This asymmetry is intentional: Channel 1 targets ultra-precise core rails, while Channel 2 serves auxiliary or less-critical supplies.
How does the DTR (Detect Transient) feature reduce overshoot in the LTC3838EUHF#PBF?
The DTR feature monitors load-release events by sensing voltage drop on DTR1/DTR2 pins. When the pin voltage falls below half of INTVCC, the LTC3838EUHF#PBF immediately disables the bottom gate (BG) driver, allowing inductor current to decay faster through freewheeling paths. This cuts VOUT overshoot by up to 60% compared to standard operation - validated in Figure G02–G04 of the datasheet.
Can the LTC3838EUHF#PBF operate with only one channel enabled?
Yes - the LTC3838EUHF#PBF supports independent channel control via RUN1 and RUN2 pins. Driving either RUN pin below 0.8V disables its associated channel's bias supplies and gate drivers while the other remains fully operational. Quiescent current drops to ~2mA (vs. ~3mA dual-channel), enabling flexible power partitioning in multi-rail systems.
What is the purpose of the VRNG1 and VRNG2 pins on the LTC3838EUHF#PBF?
VRNG1 and VRNG2 set the maximum current sense threshold (VSENSE(MAX)) for Channels 1 and 2 respectively. Applying 0.6V–2V to each pin scales the sense range linearly: (VSENSE+ – VSENSE–)MAX = 0.05 × VRNG. Tying VRNG to SGND or INTVCC selects fixed 30mV or 50mV ranges - enabling optimization of current limit accuracy and noise rejection per rail.
LTC3838EUHF#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 38-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 38V
- Frequency - Switching:
- 200kHz ~ 2MHz
- Duty Cycle (Max):
- -
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Enable, Frequency Control, Phase Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 38-QFN (5x7)
LTC3838EUHF#PBF FAQ
1.How can I place an order for LTC3838EUHF#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3838EUHF#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3838EUHF#PBF reliable?
The price and inventory of LTC3838EUHF#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3838EUHF#PBF is usually 5 days.
3.What payment methods are accepted for LTC3838EUHF#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3838EUHF#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3838EUHF#PBF?
LTC3838EUHF#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3838EUHF#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3838EUHF#PBF?
For technical support, including LTC3838EUHF#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3838EUHF#PBF requirements.
6.How does Aetrix verify that LTC3838EUHF#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3838EUHF#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3838EUHF#PBF meets industry standards.
7.What is the process for return or replacement of LTC3838EUHF#PBF?
All LTC3838EUHF#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3838EUHF#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3838EUHF#PBF part is unused and in its original packaging.
Return procedure for LTC3838EUHF#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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