Analog Devices Inc. LTC3855IUJ#PBF
- Part No.:
- LTC3855IUJ#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
LTC3855IUJ#PBF.pdf
- Description:
- IC REG CTRLR BUCK 40QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3855IUJ#PBF from Analog Devices (formerly Linear Technology) is a dual, 180° out-of-phase, current-mode synchronous step-down DC/DC controller driving all-N-channel MOSFET stages. It features differential remote sensing, programmable current sense thresholds (30/50/75 mV), 0.6 V ±0.75% reference accuracy, and supports up to 12-phase operation via CLKOUT/PHASMD. Used in high-current server VRMs delivering 1.2 V/15 A and 1.8 V/15 A outputs from 12 V intermediate bus.
For engineers reviewing the LTC3855IUJ#PBF datasheet, LTC3855IUJ#PBF pinout, LTC3855IUJ#PBF application, or LTC3855IUJ#PBF equivalent, key selection criteria include phase-lockable 250–770 kHz switching frequency, DCR temperature compensation, dual independent power-good signals, and QFN-40 package thermal performance at 125°C junction temperature.
Technical Context
The LTC3855IUJ#PBF implements two independent PolyPhase® current-mode control loops with shared oscillator synchronization capability. Each channel uses a transconductance error amplifier (gm = 2 mmho), programmable ITH-based current limit, and precision 0.6 V feedback reference with ±0.75% accuracy over –40°C to 125°C.
Its differential remote sense amplifier (gain = 0.998–1.002 V/V, GBW = 3 MHz, slew rate = 2 V/µs) enables accurate load regulation down to 0.6 V output with ±10% PGOOD window, while integrated DCR temperature compensation (via ITEMP1/ITEMP2 pins) maintains current-sense accuracy across thermal gradients in multiphase inductor banks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5 V to 38 V - supports 5 V, 12 V, and 24 V intermediate bus systems without external regulators. |
| Output Voltage Range | 0.6 V to 12.5 V - covers core logic (1.2 V), I/O (1.8 V), and auxiliary rails (3.3 V, 5 V) with true remote sensing down to 0.6 V. |
| Switching Frequency | 250 kHz to 770 kHz - adjustable via FREQ pin current (10 µA) for EMI optimization and inductor size trade-offs. |
| Current Sense Threshold | 30 / 50 / 75 mV - selectable per channel via ILIM1/ILIM2 pins to match DCR or discrete RSENSE with minimal power loss. |
| Reference Accuracy | ±0.75% at 0.6 V - ensures tight output regulation under line/load/temperature variation for CPU/GPU VRMs. |
| Junction Temperature Range | –40°C to +125°C - qualified for industrial and telecom base station environments with validated thermal derating. |
| Package | 40-pin 6 mm × 6 mm QFN with exposed pad - provides low θJA = 33°C/W for high-power density layouts. |
Pinout & Package
Package: 40-lead (6 mm × 6 mm) plastic QFN with exposed SGND pad (Pin 41), rated for –40°C to +125°C operating junction temperature.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| TG1, TG2 | Top gate driver outputs | Drive N-channel high-side MOSFET gates with 2.6 Ω pull-up / 1.5 Ω pull-down RDS(ON); require bootstrap capacitors tied to BOOST1/BOOST2. |
| BG1, BG2 | Bottom gate driver outputs | Drive N-channel low-side MOSFET gates with 2.4 Ω pull-up / 1.1 Ω pull-down RDS(ON); connect directly to PGND1/PGND2. |
| SENSE1+, SENSE1– SENSE2+, SENSE2– | Dual current sense inputs | Accept DCR or resistor-based sensing; bias current ±1 µA enables low-loss layout with <100 mΩ sense elements. |
| VFB1, VFB2 | Error amplifier feedback inputs | Monitor regulated output voltage via resistive divider; input bias current –15 nA minimizes divider error. |
| DIFFP, DIFFN, DIFFOUT | Differential remote sense amplifier | Enable Kelvin sensing at load point: DIFFP connects to remote VOUT+, DIFFN to capacitor ground, DIFFOUT feeds VFBx via divider. |
| CLKOUT, PHASMD | Multiphase synchronization interface | CLKOUT provides phase-adjustable clock (60°/90°/120°); PHASMD selects internal phase relationship (0°/180°/240°) for multi-controller stacking. |
| ILIM1, ILIM2 | Current limit threshold select | Set max sense voltage to 30 mV (GND), 50 mV (float), or 75 mV (INTVCC) - critical for DCR vs RSENSE design choice. |
| TK/SS1, TK/SS2 | Soft-start / tracking inputs | Internal 1.2 µA current charges external capacitor for linear VOUT ramp; also accepts master VFB for supply sequencing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual 180° phased controllers | Reduces input ripple current by >70%, enabling smaller bulk capacitance and lower EMI in high-current VRMs. |
| Programmable DCR temperature compensation | Uses external NTC thermistors on ITEMP1/ITEMP2 to correct DCR drift, maintaining ±3% current limit accuracy over temperature. |
| True remote sensing differential amplifier | 0.998–1.002 V/V gain and 2 mV offset enable sub-10 mV load regulation error at 1.2 V output with 100 mV drop across PCB traces. |
| Three light-load operating modes | Burst Mode (floating MODE/PLLIN), pulse-skipping (INTVCC), or forced continuous (GND) - selectable per system noise/efficiency requirements. |
| Dual independent power-good signals | PGOOD1/PGOOD2 open-drain outputs assert after 20 µs delay when VFB enters ±10% window - enables sequenced power-up of FPGA/CPU subsystems. |
Applications
| Server CPU Voltage Regulator | Telecom Baseband Power Supply |
|---|---|
Use Scenario: Delivering 1.2 V @ 15 A to dual-core Xeon-class processors with dynamic load steps up to 5 A/µs. IC Role / Device Role / Timing Role: Dual-phase synchronous buck controller managing top/bottom N-MOSFETs, coordinating phase timing via CLKOUT to minimize input ripple. Use Value: 95% peak efficiency at full load and Burst Mode operation extending battery backup runtime during idle periods. | Use Scenario: Generating isolated 3.3 V and 1.8 V rails for LTE baseband ASICs in outdoor cabinets with –40°C to +75°C ambient. IC Role / Device Role / Timing Role: Dual-channel controller with differential remote sensing compensating for 50 mΩ PCB trace resistance between VRM and load. Use Value: ±0.75% reference accuracy and DCR temperature compensation maintain <±15 mV output deviation across temperature and load. |
| Industrial PLC I/O Module | Medical Imaging Sensor Bias Supply |
Use Scenario: Providing tightly regulated 5 V and 3.3 V for analog sensor interfaces and digital logic in factory-floor PLCs. IC Role / Device Role / Timing Role: Dual-output controller with independent RUN1/RUN2 shutdown and soft-start sequencing via TK/SS pins. Use Value: Independent channel control enables safe hot-swap of I/O modules without disrupting main system power. | Use Scenario: Supplying low-noise 1.5 V bias to CMOS image sensor arrays in portable ultrasound devices. IC Role / Device Role / Timing Role: Forced continuous mode (MODE/PLLIN = GND) eliminates Burst Mode switching artifacts that could couple into analog imaging paths. Use Value: Sub-10 mVpp output ripple and <10 µV/°C thermal drift ensure pixel-level signal integrity during real-time scanning. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP8765GL-10-Z | Single-channel, 6 A integrated power stage; no differential remote sense or DCR tempco; fixed 500 kHz fSW. | Suitable for space-constrained single-rail designs but lacks multiphase scalability and precision remote sensing. | Select MP8765GL-10-Z only for cost-sensitive, low-current (<6 A) applications where phase interleaving and Kelvin sensing are unnecessary. |
| ISL95812IRZ | Triple-phase capable, supports Intel VR12.5/VR12.6 protocols; includes SMBus interface; no QFN-40 package option. | Targeted at client CPU VRMs with dynamic VID control; requires external PMBus host and adds protocol overhead. | Choose ISL95812IRZ when compliance with Intel VR12.6 dynamic voltage identification and telemetry reporting is mandatory. |
Compared with MP8765GL-10-Z and ISL95812IRZ, the LTC3855IUJ#PBF uniquely combines dual independent channels, differential remote sensing, DCR temperature compensation, and 125°C operation in a compact QFN-40 - making it optimal for high-reliability, high-current industrial and telecom VRMs where layout flexibility and thermal robustness are critical.
Availability
LTC3855IUJ#PBF is available at Aetrix Electronics and suitable for server CPU voltage regulation, telecom baseband power supplies, and industrial PLC I/O modules requiring stable component supply and long-term lifecycle support.
Supply support for LTC3855IUJ#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full technical and manufacturing continuity for the LTC portfolio, including rigorous AEC-Q200-aligned reliability testing and extended product lifecycles.
The LTC3855IUJ#PBF belongs to Linear's high-performance power controller family designed for demanding multiphase DC/DC conversion in computing, communications, and industrial infrastructure - emphasizing precision regulation, thermal resilience, and layout flexibility.
FAQ
What is the maximum operating junction temperature for the LTC3855IUJ#PBF?
The LTC3855IUJ#PBF is rated for a maximum junction temperature of +125°C, verified across the full –40°C to +125°C operating range per datasheet specifications. Its QFN-40 package has θJA = 33°C/W, enabling reliable operation in enclosed telecom chassis or industrial enclosures without forced airflow when power dissipation remains within thermal limits calculated using TJ = TA + (PD × 33°C/W).
How does the LTC3855IUJ#PBF implement differential remote sensing?
The LTC3855IUJ#PBF implements differential remote sensing using dedicated DIFFP, DIFFN, and DIFFOUT pins. DIFFP connects directly to the remote positive load terminal, DIFFN to the local output capacitor ground, and DIFFOUT feeds back into VFB1 or VFB2 through an external resistor divider. The integrated differential amplifier delivers 0.998–1.002 V/V gain and 2 mV offset, correcting for IR drop across PCB traces to achieve <±10 mV regulation error at 1.2 V output.
Can the LTC3855IUJ#PBF be configured for single-channel operation?
Yes, the LTC3855IUJ#PBF supports single-channel operation by disabling one controller: tie RUN2 to SGND to shut down Channel 2 while retaining full functionality on Channel 1. All Channel 1 pins (TG1, BG1, SENSE1+, etc.) remain active, and the device retains its full suite of features - including differential sensing, DCR temperature compensation, and programmable current limit - for the enabled channel.
What are the supported switching frequency ranges and how is frequency set?
The LTC3855IUJ#PBF supports 250 kHz to 770 kHz via the FREQ pin, which sources a precise 10 µA current. A resistor RFREQ from FREQ to SGND sets fSW ≈ 10 µA × RFREQ / 12 kΩ. For example, RFREQ = 600 kΩ yields ~500 kHz. Alternatively, applying a DC voltage (0–2.4 V) directly to FREQ allows fine-tuning - 0 V gives ~250 kHz, 1.2 V gives ~500 kHz, and ≥2.4 V gives ~770 kHz.
Does the LTC3855IUJ#PBF support external clock synchronization?
Yes, the LTC3855IUJ#PBF supports external clock synchronization via the MODE/PLLIN pin. When a clean clock signal (250–770 kHz) is applied to MODE/PLLIN, both channels enter forced continuous mode and the internal PLL locks to the external source. This enables deterministic phase alignment across multiple LTC3855IUJ#PBF controllers in high-current 12-phase systems, eliminating beat frequencies and simplifying EMI filtering.
LTC3855IUJ#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 38V
- Frequency - Switching:
- 250kHz ~ 770kHz
- Duty Cycle (Max):
- 95%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Phase Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 40-QFN (6x6)
LTC3855IUJ#PBF FAQ
1.How can I place an order for LTC3855IUJ#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3855IUJ#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3855IUJ#PBF reliable?
The price and inventory of LTC3855IUJ#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3855IUJ#PBF is usually 5 days.
3.What payment methods are accepted for LTC3855IUJ#PBF?
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4.How is shipping managed for LTC3855IUJ#PBF?
LTC3855IUJ#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3855IUJ#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3855IUJ#PBF?
For technical support, including LTC3855IUJ#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3855IUJ#PBF requirements.
6.How does Aetrix verify that LTC3855IUJ#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3855IUJ#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3855IUJ#PBF meets industry standards.
7.What is the process for return or replacement of LTC3855IUJ#PBF?
All LTC3855IUJ#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3855IUJ#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3855IUJ#PBF part is unused and in its original packaging.
Return procedure for LTC3855IUJ#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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