Analog Devices Inc. LTC3856EUH#PBF
- Part No.:
- LTC3856EUH#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LTC3856EUH#PBF.pdf
- Description:
- IC REG CTRLR BUCK 32WFQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3856EUH#PBF from Analog Devices (formerly Linear Technology) is a dual-channel PolyPhase® synchronous step-down DC/DC controller driving all-N-channel MOSFET stages for high-current 1.5V/50A power delivery. It features true remote differential voltage sensing, DCR or RSENSE current sensing with temperature compensation, and phase-lockable fixed-frequency operation up to 770kHz across a 4.5V–38V input range.
For engineers reviewing the LTC3856EUH#PBF datasheet, LTC3856EUH#PBF pinout, LTC3856EUH#PBF application, or LTC3856EUH#PBF equivalent, this controller supports precise active voltage positioning (AVP), programmable burst mode or stage shedding for light-load efficiency, and stackable 2- to 12-phase configurations in telecom, industrial, and computer power systems.
Technical Context
The LTC3856EUH#PBF implements a constant-frequency current-mode control architecture with independent per-channel peak-current sensing via SENSE1+/– and SENSE2+/– inputs. Its dual-phase interleaved operation reduces input/output ripple and EMI while enabling up to 12-phase scaling through CLKOUT/PLLIN synchronization.
It integrates a high-speed differential amplifier (gain = 0.998–1.002 V/V, PSRR = 100dB) for remote output sensing, programmable DCR temperature compensation (via ITEMP), and a dedicated AVP pin for load-line slope programming-functionality only active when DIFFAMP is used and VOUT ≤ 3.3V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5V to 38V - supports 5V, 12V, and 24V intermediate bus rails and wide battery chemistries. |
| Output Voltage Range | 0.6V to 3.3V with differential amplifier; 0.6V to 5V without - enables core voltage regulation for CPUs, FPGAs, and ASICs. |
| Reference Accuracy | ±0.75% at 0.6V - ensures tight output regulation under line/load/temperature variation. |
| Switching Frequency | 250kHz to 770kHz (programmable via FREQ pin) - balances efficiency, size, and EMI for high-density designs. |
| Current Sensing | RSENSE or DCR-based with programmable ILIM (GND/FLOAT/INTVCC) - provides three selectable max sense thresholds (25–84mV) for flexible design margining. |
| Efficiency | Up to 95% at 1.5V/50A - achieved via low-RDS(ON) gate drivers (TG RUP = 2.6Ω, BG RDOWN = 1.1Ω) and out-of-phase dual-phase operation. |
| Package | 32-pin (5mm × 5mm) QFN with exposed SGND/PGND pad - optimized for thermal dissipation (θJA = 34°C/W) and compact layout. |
Pinout & Package
Package: 32-lead (5mm × 5mm) plastic QFN (UH package) with exposed SGND/PGND pad (Pin 33) requiring PCB soldering for thermal and electrical performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TG1, TG2 | Top gate driver outputs | Floating N-channel gate drivers with 2.6Ω pull-up / 1.5Ω pull-down RDS(ON); require external bootstrap capacitors. |
| BG1, BG2 | Bottom gate driver outputs | Ground-referenced N-channel gate drivers with 2.4Ω pull-up / 1.1Ω pull-down RDS(ON); drive synchronous rectifiers. |
| SENSE1+, SENSE1− SENSE2+, SENSE2− |
Per-channel current sense inputs | Differential inputs for DCR or RSENSE sensing; support temperature-compensated current limit setting via ITEMP. |
| DIFFP, DIFFN, DIFFOUT | Remote differential amplifier terminals | Enable true Kelvin sensing: DIFFP connects to load, DIFFN to output capacitor negative, DIFFOUT feeds VFB via divider. |
| VFB | Error amplifier feedback input | Regulates output to 0.6V reference; accepts feedback from DIFFOUT (remote) or direct resistor divider (local). |
| TK/SS | Soft-start/tracking control | 1.25µA internal current charges external capacitor for linear VOUT ramp; also supports supply tracking via resistor divider. |
| MODE | Operating mode selection | GND = forced continuous; FLOAT = Burst Mode; INTVCC = Stage Shedding - selects light-load efficiency strategy. |
| ILIM | Current sense threshold select | Three-level programming (GND/FLOAT/INTVCC) sets max sense voltage to 25/50/75mV (E-grade) for overcurrent protection tuning. |
| AVP | Active voltage positioning | Resistor to DIFFP sets load-line slope; only functional with differential sensing and VOUT ≤ 3.3V. |
| PLLIN, CLKOUT | Phase synchronization I/O | Allows multi-phase stacking: PLLIN accepts external clock; CLKOUT provides phase-adjustable output (60°/90°/120°) via PHASMD. |
Key Features
| Feature | Design Value |
|---|---|
| PolyPhase® dual-channel control | Reduces input/output capacitance by √2 and cuts RMS input ripple current by 50%, lowering EMI and bulk capacitor count. |
| True remote differential sensing | 0.998–1.002 V/V gain and 100dB PSRR enable sub-10mV DC load regulation at point-of-load despite PCB IR drop. |
| Programmable DCR temperature compensation | ITEMP pin sinks 9–11µA to bias external NTC network, maintaining stable current limit across –40°C to 125°C junction range. |
| Stackable 2–12-phase operation | CLKOUT phase shift (60°/90°/120°) and PLLIN sync allow seamless expansion beyond two controllers without external timing ICs. |
| Active Voltage Positioning (AVP) | Programmable load-line slope via AVP–DIFFP resistor ensures dynamic VOUT droop during load transients matches CPU power delivery requirements. |
Applications
| Telecom Rectifier Modules | High-Performance FPGA Power |
|---|---|
|
Use Scenario: 48V-to-1.2V conversion delivering 60A+ to baseband processing units in 5G macro radios. IC Role / Device Role / Timing Role: Dual-phase synchronous buck controller managing parallel MOSFET stages with interleaved switching to minimize input ripple and heat generation. Use Value: Achieves >94% efficiency at full load and <15mV load regulation via remote sensing-critical for meeting GR-1089 EMI and thermal limits. |
Use Scenario: Core voltage regulation for Xilinx Versal ACAPs requiring fast transient response and AVP-compliant droop behavior. IC Role / Device Role / Timing Role: Primary controller implementing active voltage positioning with programmable load-line slope and 770kHz switching for minimal output capacitance. Use Value: AVP function ensures VOUT drops predictably under load steps, preventing overshoot and satisfying FPGA VCCINT specification margins. |
| Industrial PLC CPU Power | Medical Imaging Subsystem Supply |
|
Use Scenario: 24V-to-1.8V conversion powering ARM Cortex-A53 clusters in ruggedized programmable logic controllers. IC Role / Device Role / Timing Role: Dual-phase controller operating in Stage Shedding mode to maintain >90% efficiency from 1A to 40A load range. Use Value: Dynamic phase shedding eliminates light-load inefficiency penalties common in fixed-phase converters, extending system uptime in intermittent workloads. |
Use Scenario: Precision 3.3V/20A supply for analog front-end ADCs and clock distribution in MRI signal chain modules. IC Role / Device Role / Timing Role: Controller using differential sensing and low-noise 5V INTVCC regulator to suppress switching noise coupling into sensitive analog circuitry. Use Value: 100dB PSRR on DIFFAMP and dedicated SGND/PGND separation reduce conducted noise below 10µV RMS, preserving SNR in 16-bit data acquisition. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2940AGQ-DC | Integrated MOSFETs (40V/60A), fixed 600kHz frequency, no DCR tempco or AVP. | Suitable for space-constrained designs where board area > efficiency optimization; lacks remote sensing precision. | Select when BOM simplification and footprint reduction outweigh need for programmable light-load modes or AVP. |
| ISL95836IRZ | Single-chip 3-phase controller (no stacking), supports Intel VR13/VR14 protocols, no differential amplifier. | Targeted at x86 CPU VR applications with SMBus interface; not suitable for custom FPGA/ASIC supplies. | Choose only for Intel platform compliance; incompatible with non-Intel AVP or PolyPhase stacking requirements. |
Compared with MP2940AGQ-DC and ISL95836IRZ, the LTC3856EUH#PBF uniquely combines stackable PolyPhase architecture, true differential remote sensing, and AVP-enabling higher accuracy, lower noise, and scalable multi-phase designs unattainable with integrated or single-protocol alternatives.
Availability
LTC3856EUH#PBF is available at Aetrix Electronics and suitable for telecom rectifier modules, high-performance FPGA power systems, and industrial PLC CPU supplies requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LTC3856EUH#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance power management portfolio, emphasizing precision, efficiency, and reliability for demanding analog-intensive applications.
The LTC3856EUH#PBF belongs to Linear's PolyPhase® controller family, designed specifically for high-current, low-voltage DC/DC conversion in computing, communications, and industrial systems where thermal density, transient response, and multi-phase scalability are critical.
FAQ
What is the maximum supported switching frequency for the LTC3856EUH#PBF?
The LTC3856EUH#PBF supports a programmable switching frequency from 250kHz to 770kHz, set via the FREQ pin using a resistor-to-ground or DC voltage. At VFREQ ≥ 2.4V, the nominal frequency reaches 770kHz (typical), enabling compact magnetics and faster transient response in high-density power designs.
Does the LTC3856EUH#PBF support remote voltage sensing, and how is it implemented?
Yes, the LTC3856EUH#PBF implements true remote sensing via an integrated differential amplifier with DIFFP, DIFFN, and DIFFOUT pins. DIFFP connects directly to the load, DIFFN to the output capacitor negative terminal, and DIFFOUT feeds the VFB pin through a resistive divider-enabling sub-10mV DC regulation accuracy despite PCB trace resistance.
How does the LTC3856EUH#PBF achieve high light-load efficiency?
The LTC3856EUH#PBF achieves high light-load efficiency through three selectable operating modes: Burst Mode (pin floating), Stage Shedding (MODE = INTVCC), or forced continuous conduction (MODE = GND). Stage Shedding dynamically disables one phase below ~25% load, cutting gate drive losses and boosting efficiency above 90% at 1A–5A loads.
What is the purpose of the AVP pin on the LTC3856EUH#PBF, and when is it active?
The AVP pin on the LTC3856EUH#PBF programs active voltage positioning load-line slope for CPU/FPGA core supplies. It is only functional when the differential amplifier is enabled (i.e., DIFFP/DIFFN connected) and VOUT ≤ 3.3V. A resistor between AVP and DIFFP sets the droop characteristic to match processor VR specifications.
Can multiple LTC3856EUH#PBF controllers be synchronized, and how is phase alignment controlled?
Yes, multiple LTC3856EUH#PBF controllers can be synchronized via the PLLIN and CLKOUT pins. The PLLIN pin accepts an external clock to lock all devices, while CLKOUT's phase (60°, 90°, or 120°) is selected by pulling PHASMD to SGND, FLOAT, or INTVCC-enabling precise interleaving for 2–12-phase systems without external timing components.
LTC3856EUH#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4.5V ~ 38V
- Frequency - Switching:
- 250kHz ~ 770kHz
- Duty Cycle (Max):
- 94%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Phase Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-QFN (5x5)
LTC3856EUH#PBF FAQ
1.How can I place an order for LTC3856EUH#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3856EUH#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3856EUH#PBF reliable?
The price and inventory of LTC3856EUH#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3856EUH#PBF is usually 5 days.
3.What payment methods are accepted for LTC3856EUH#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3856EUH#PBF transactions.
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4.How is shipping managed for LTC3856EUH#PBF?
LTC3856EUH#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3856EUH#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3856EUH#PBF?
For technical support, including LTC3856EUH#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3856EUH#PBF requirements.
6.How does Aetrix verify that LTC3856EUH#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3856EUH#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3856EUH#PBF meets industry standards.
7.What is the process for return or replacement of LTC3856EUH#PBF?
All LTC3856EUH#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3856EUH#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3856EUH#PBF part is unused and in its original packaging.
Return procedure for LTC3856EUH#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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