My Inquiry
My Account
Analog Devices Inc. LTC3858IUH#PBF
- Part No.:
- LTC3858IUH#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LTC3858IUH#PBF.pdf
- Description:
- IC REG CTRLR BUCK 32QFN
- Quantity:
- Payment:
- Shipping:
Inventory:1,112
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LTC3858IUH#PBF from Analog Devices (formerly Linear Technology) is a dual-phase, synchronous step-down DC/DC controller driving two independent N-channel MOSFET stages. It delivers 0.8V–24V output voltage per channel, supports 4V–38V input, operates at 75kHz–850kHz with phase-lock capability, and achieves 170μA quiescent current in single-channel sleep mode-enabling high-efficiency power conversion in battery-powered digital systems.
For engineers reviewing the LTC3858IUH#PBF datasheet, LTC3858IUH#PBF pinout, LTC3858IUH#PBF application, or LTC3858IUH#PBF equivalent, key selection considerations include out-of-phase dual-channel operation for reduced input ripple, OPTI-LOOP® compensation for wide capacitor ESR tolerance, selectable light-load modes (Burst Mode®, pulse-skipping, forced continuous), and integrated short-circuit latch-off with soft-start programmability.
Technical Context
The LTC3858IUH#PBF implements a constant-frequency current-mode architecture with two fully independent control loops operating 180° out of phase to minimize input capacitor RMS current and system noise. Each channel features separate ITH error amplifier outputs, VFB feedback inputs, SS soft-start pins, and PGOOD indicators-enabling asymmetric output configurations (e.g., 3.3V/5A and 8.5V/3.5A).
It integrates dual gate drivers (TG/BG) with 2.5Ω pull-up and 1.5Ω pull-down on top-side drivers, supports RSENSE or DCR current sensing via differential SENSE± inputs, and includes an internal 5.1V LDO (INTVCC) powered either from VIN or external EXTVCC ≥4.7V-allowing efficient self-biasing from one of its own regulated outputs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 4V to 38V - supports wide-input industrial, automotive, and battery-based intermediate bus applications. |
| VOUT Range | 0.8V to 24V per channel - enables generation of core, I/O, and auxiliary rails from a single controller. |
| IQ (Sleep, 1 ch) | 170μA typical - extends runtime in always-on, low-power battery systems without compromising regulation. |
| fSW Range | 75kHz–850kHz (phase-lockable) - allows EMI optimization and compact magnetics design across diverse loads. |
| Duty Cycle Max | 99.4% - supports ultra-low dropout operation near VIN = VOUT, critical for high-efficiency buck conversion at low ΔV. |
| Current Sensing | RSENSE or DCR - provides flexibility in loss vs. accuracy trade-offs and eliminates need for sense resistors in some designs. |
| Package | 32-lead 5mm × 5mm QFN with exposed thermal pad - delivers high power density and 34°C/W θJA for thermally constrained PCBs. |
Pinout & Package
Package: 32-lead (5mm × 5mm) plastic QFN with exposed SGND pad (Pin 33), rated for –40°C to +125°C junction temperature.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SENSE1–, SENSE2– (1, 9) | Differential current sense (–) | Reference input for current comparator; supplies bias current when > INTVCC – 0.5V. |
| FREQ (2) | Oscillator frequency control | Resistor-to-GND sets 50–900kHz; GND = 350kHz, INTVCC = 535kHz. |
| PHASMD (3) | Phase relationship selector | Configures TG2/CLKOUT phase offset relative to TG1: 180°/90° (float), 180°/60° (GND), or 240°/120° (INTVCC). |
| CLKOUT (4) | Master clock output | Drives daisy-chained controllers; swing = INTVCC to SGND; synchronized to TG1 rising edge. |
| PLLIN/MODE (5) | Synchronization & light-load mode | Accepts external clock for PLL sync; GND = Burst Mode®, INTVCC = forced continuous, mid-voltage = pulse-skip. |
| SGND (6, 33) | Small-signal ground | Common analog reference for both channels; exposed pad must be soldered for thermal performance. |
| RUN1, RUN2 (7, 8) | Independent enable/disable | Below 1.23V disables respective channel; both <0.7V enters 8μA shutdown. |
| BOOST1, BOOST2 (17, 24) | Top-gate bootstrap supply | Swing = INTVCC to (VIN + INTVCC); requires external bootstrap capacitor and Schottky diode. |
| TG1, TG2 (15, 26) | Top N-MOSFET gate drive | Floating driver output; swing = INTVCC – 0.5V superimposed on SW node voltage. |
| BG1, BG2 (18, 23) | Bottom N-MOSFET gate drive | Ground-referenced driver; swing = 0V to INTVCC; drives synchronous rectifier FETs. |
| SW1, SW2 (16, 25) | Switch node connection | Connects to inductor high-side terminal and BOOST capacitor; carries high dv/dt switching waveform. |
| PGND (21) | Power ground return | Return path for bottom FET sources and CIN(–); must be routed separately from SGND. |
| VIN (22) | Main input supply | Primary power source for INTVCC LDO and internal circuitry; bypass to SGND with ceramic capacitor. |
| EXTVCC (20) | External bias input | Enables alternate 5.1V LDO when >4.7V; allows efficient self-powering from regulated output rail. |
| INTVCC (19) | Internal LDO output | 5.1V ±3%, powers gate drivers and control logic; requires ≥4.7μF low-ESR ceramic decoupling. |
| VFB1, VFB2 (11, 31) | Feedback voltage input | Compares remote output voltage (via resistor divider) to 0.800V reference; ±10% PGOOD threshold. |
| ITH1, ITH2 (12, 30) | Error amplifier output | Controls peak inductor current limit; higher voltage increases current trip point linearly. |
| SS1, SS2 (13, 29) | Soft-start / latch-off timer | Internal 1μA pull-up ramps voltage; used for controlled VOUT ramp and short-circuit timeout (2V arming, 1.5V latch-off). |
| PGOOD1, PGOOD2 (14, 27) | Open-drain power-good flag | Pulled low when VFB deviates >±10% from setpoint; requires external pull-up resistor. |
| ILIM (28) | Current limit range select | GND/FLOAT/INTVCC selects max sense threshold: 22/43/64mV - sets full-scale current limit sensitivity. |
Key Features
| Feature | Design Value |
|---|---|
| Out-of-phase dual-channel operation | Reduces input capacitor RMS current by up to 30% and suppresses power supply-induced noise in shared input rails. |
| OPTI-LOOP® compensation | Allows stable loop response across wide ranges of output capacitance (10μF–1000μF) and ESR (1mΩ–100mΩ) without re-tuning. |
| Programmable light-load behavior | Three distinct modes: Burst Mode® (highest efficiency <10mA), pulse-skipping (low-noise), or forced continuous (lowest output ripple). |
| Short-circuit protection with latch-off | Independent SS-pin-based timer arms after VOUT reaches regulation; discharges at 9μA during fault to trigger shutdown within ~100ms–1s depending on CSS. |
| Dropout detection & recovery | Monitors duty cycle; forces periodic bottom-FET conduction to recharge bootstrap capacitors when VIN ≈ VOUT, preventing gate-drive collapse. |
Applications
| Automotive Infotainment Power Supply | Portable Medical Diagnostic Device |
|---|---|
Use Scenario: Dual-rail power for SoC (1.2V core, 3.3V I/O) and display backlight (8.5V) in head-unit under 9V–16V battery input with cold-crank immunity. IC Role / Device Role / Timing Role: Dual-phase synchronous buck controller delivering isolated, tightly regulated outputs with phase interleaving to reduce EMI and input ripple. Use Value: 170μA sleep IQ extends standby time; 99.4% max duty cycle maintains regulation during 6V cold-crank; PGOOD flags enable safe system boot sequencing. | Use Scenario: Battery-powered ultrasound handheld requiring low-noise 3.3V analog front-end and 5V digital subsystem with >12-hour runtime. IC Role / Device Role / Timing Role: High-efficiency dual-output controller enabling Burst Mode® operation below 5mA load to minimize quiescent loss while maintaining fast transient response. Use Value: OPTI-LOOP® ensures stability with polymer tantalum output caps; independent soft-start prevents inrush into sensitive analog circuits; latch-off protects against probe short events. |
| Industrial IoT Edge Gateway | Telecom Distributed Power System |
Use Scenario: 48V PoE++-powered gateway generating 12V (Ethernet PHY), 5V (CPU), and 3.3V (sensor interface) from single intermediate bus. IC Role / Device Role / Timing Role: Dual-channel controller configured as two independent converters (12V/5V and 5V/3.3V) sharing input stage but with separate feedback and protection. Use Value: Wide 4V–38V input accommodates PoE voltage drop; EXTVCC option allows INTVCC to be powered from 12V rail, improving overall system efficiency by 1–2%. | Use Scenario: 24V/48V telecom shelf supplying multiple board-level rails (e.g., 12V, 5V, 3.3V) with strict hold-up time and EMI requirements. IC Role / Device Role / Timing Role: Phase-locked dual controller synchronizing to system clock to eliminate beat frequencies and simplify EMI filter design across multiple boards. Use Value: CLKOUT and PLLIN enable deterministic multi-phase timing; 75kHz–850kHz sync range matches common telecom clocks; 32-lead QFN fits dense backplane layouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2918GL-Z | Single-package dual controller with integrated MOSFET drivers only; no external gate drive; fixed 0.6V reference; no EXTVCC option. | Lower BOM count but limited to ≤12V input and ≤5A per phase; lacks phase modulation and CLKOUT for multi-controller sync. | Select MP2918GL-Z for cost-sensitive, lower-power applications where integration outweighs flexibility and wide-VIN support. |
| LTC3838EUH#PBF | Same family, pin-compatible dual controller but with fixed 50kHz–900kHz frequency range (no PLL sync), no CLKOUT, and no PHASMD pin-only 180° phase shift. | Supports identical VIN/VOUT ranges and IQ, but cannot synchronize to external clocks or configure non-180° phase offsets for advanced noise cancellation. | Select LTC3838EUH#PBF when phase synchronization is unnecessary and simpler layout is prioritized over system-level EMI coordination. |
Compared with MP2918GL-Z and LTC3838EUH#PBF, the LTC3858IUH#PBF uniquely combines phase-lockable frequency, programmable phase offset, CLKOUT daisy-chaining, and EXTVCC biasing-making it optimal for high-performance, multi-rail, noise-sensitive systems requiring precise timing control and thermal efficiency.
Availability
LTC3858IUH#PBF is available at Aetrix Electronics and suitable for automotive infotainment, portable medical diagnostics, and industrial IoT edge gateways requiring stable component supply, extended temperature operation (–40°C to +125°C), and long-term production continuity.
Supply support for LTC3858IUH#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains its high-performance power management portfolio with rigorous automotive and industrial qualification standards.
The LTC3858IUH#PBF belongs to Linear's PolyPhase® dual/multi-phase controller family, designed specifically for high-efficiency, low-noise, and thermally optimized DC/DC conversion in space-constrained, high-reliability applications.
FAQ
What is the minimum input voltage supported by the LTC3858IUH#PBF?
The LTC3858IUH#PBF supports a minimum input voltage of 4V across its full operating temperature range (–40°C to +125°C). This enables reliable operation from partially discharged 12V lead-acid batteries or regulated 5V intermediate buses. Operation below 4V is not guaranteed and may result in UVLO activation or unstable regulation.
How does the LTC3858IUH#PBF achieve 170μA quiescent current?
The LTC3858IUH#PBF achieves 170μA quiescent current in single-channel sleep mode through adaptive biasing of internal amplifiers, clock gating of unused control loops, and optimized gate driver precharge circuits. This specification is measured with one RUN pin high and the other low, VFB held at 0.83V, and no switching activity-ensuring minimal battery drain in always-on standby applications.
Can the LTC3858IUH#PBF drive MOSFETs directly without external drivers?
Yes, the LTC3858IUH#PBF integrates high-current gate drivers capable of directly driving standard N-channel MOSFETs: TG1/TG2 deliver 2.5Ω pull-up / 1.5Ω pull-down, and BG1/BG2 deliver 2.4Ω pull-up / 1.1Ω pull-down. These drivers support typical gate charges up to 50nC at 500kHz without external buffers-eliminating need for discrete drivers in most medium-power applications.
What protection features does the LTC3858IUH#PBF include for short-circuit conditions?
The LTC3858IUH#PBF includes dual independent short-circuit protections: (1) Output latch-off triggered when SS pin voltage falls below 1.5V after arming above 2V, and (2) foldback current limiting that progressively reduces peak current as VOUT drops below 70% of regulation-preventing thermal runaway even before latch-off activates. Both functions operate per channel without cross-talk.
Is the LTC3858IUH#PBF pin-compatible with other members of the LTC3858 family?
Yes, the LTC3858IUH#PBF shares identical pinout and footprint with LTC3858EUH#PBF and LTC3858CUH#PBF. All variants use the same 32-lead 5mm × 5mm QFN package and functionally identical silicon-differing only in temperature grade (–40°C to +125°C for 'I', 0°C to +85°C for 'E') and screening. No PCB redesign is required when upgrading between grades.
LTC3858IUH#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- Transistor Driver
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 4V ~ 38V
- Frequency - Switching:
- 105kHz ~ 835kHz, 350kHz ~ 535kHz
- Duty Cycle (Max):
- 99.4%
- Synchronous Rectifier:
- Yes
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Power Good, Soft Start
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-QFN (5x5)
LTC3858IUH#PBF FAQ
1.How can I place an order for LTC3858IUH#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3858IUH#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3858IUH#PBF reliable?
The price and inventory of LTC3858IUH#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3858IUH#PBF is usually 5 days.
3.What payment methods are accepted for LTC3858IUH#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3858IUH#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3858IUH#PBF?
LTC3858IUH#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3858IUH#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3858IUH#PBF?
For technical support, including LTC3858IUH#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3858IUH#PBF requirements.
6.How does Aetrix verify that LTC3858IUH#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3858IUH#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3858IUH#PBF meets industry standards.
7.What is the process for return or replacement of LTC3858IUH#PBF?
All LTC3858IUH#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3858IUH#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3858IUH#PBF part is unused and in its original packaging.
Return procedure for LTC3858IUH#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LTC3858IUH#PBF Tags
-
UCC28C45DR
Texas Instruments
-
UCC28C40DR
Texas Instruments
-
UCC28C43DR
Texas Instruments
-
ZXSC410E6TA
Diodes Incorporated
-
LM3524DMX/NOPB
Texas Instruments
-
LM3489MMX/NOPB
Texas Instruments
-
MIC2102YML-TR
Microchip Technology
-
LM5148RGYR
Texas Instruments
-
TL598CDR
Texas Instruments
-
LM5155DSSR
Texas Instruments
-
LM25085MYX/NOPB
Texas Instruments
-
UCC2813DTR-0
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
