Analog Devices Inc. LTC3860IUH#PBF
- Part No.:
- LTC3860IUH#PBF
- Manufacturer:
- Analog Devices Inc.
- Category:
- DC DC Switching Controllers
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LTC3860IUH#PBF.pdf
- Description:
- IC REG CTRLR BUCK 32QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LTC3860IUH#PBF from Analog Devices (formerly Linear Technology) is a dual-channel, polyphase synchronous step-down voltage mode DC/DC controller supporting up to 12-phase operation via daisy-chaining. It delivers precise current sharing across phases using lossless DCR sensing or precision resistor-based sensing, operates from 3V–24V input to 0.6V–(VCC–0.5V) output, and features ±0.75% 0.6V reference accuracy with differential remote sense for <2mV offset. It is used in high-current telecom power supplies feeding DSPs and ASICs.
For engineers reviewing the LTC3860IUH#PBF datasheet, LTC3860IUH#PBF pinout, LTC3860IUH#PBF application, or LTC3860IUH#PBF equivalent, key selection considerations include its programmable 250kHz–1.25MHz switching frequency, independent RUN1/RUN2 channel enable control, IAVG-based master-slave current balancing, TRACK/SS pin for ratiometric tracking or soft-start extension, and robust overcurrent protection with NOC detection for prebiased load startup.
Technical Context
The LTC3860IUH#PBF implements a constant-frequency voltage-mode control architecture with two independent error amplifiers (COMP1/COMP2), each driving a PWM comparator with line feedforward compensation via VINSNS. Its differential remote sense amplifier (VSNSP/VSNSN → VSNSOUT) provides unity-gain, 20MHz bandwidth, 45V/μs slew rate sensing referenced to SGND - enabling accurate load regulation despite PCB IR drop.
Current sharing is achieved through cycle-by-cycle inductor current sampling, averaging at the IAVG pin (master phase), and per-phase integrators that sum COMP voltage with current error - dynamically adjusting duty cycles to equalize phase currents. Phase relationships between channels and CLKOUT are configurable via PHSMD (0°, 60°, 90°, 120°, 180°, 240°), supporting 1-, 2-, 3-, 4-, 6-, or 12-phase topologies with up to six ICs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VIN Range | 3V to 24V - supports wide-input telecom and industrial rails without external regulators. |
| VOUT Range | 0.6V to (VCC – 0.5V) - enables sub-1V core supplies for modern processors with tight tolerance. |
| Switching Frequency | 250kHz to 1.25MHz - adjustable via FREQ pin resistor or external CLKIN; higher frequencies reduce inductor/capacitor size. |
| Reference Accuracy | ±0.75% at 0.6V - ensures ±4.5mV absolute output voltage error at 0.6V setting, critical for low-voltage logic rails. |
| Operating Temp | –40°C to +125°C junction - qualified for industrial and telecom base station environments. |
| Current Sense | Lossless DCR or precision resistor - eliminates sense resistor power loss while maintaining ±2mV input-referred offset. |
| Soft-Start Time | 2ms internal ramp - prevents inrush into prebiased loads; extendable via external capacitor on TRACK/SS pins. |
Pinout & Package
The LTC3860IUH#PBF is housed in a thermally enhanced 32-pin 5mm × 5mm QFN package with exposed pad (Pin 33) electrically connected to SGND and requiring soldering to PCB for rated thermal performance (θJA = 34°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VCC (1) | Chip supply input | 3V–5.5V bias rail; requires local 0.1–1μF ceramic bypass to SGND for stable operation. |
| FB1/FB2 (2,8) | Error amplifier inverting inputs | Connect to resistor divider from VOUT for regulation; FBx tied to VCC disables that channel's EA in multiphase mode. |
| COMP1/COMP2 (3,7) | Error amplifier outputs | Drive PWM comparators directly; must not be shorted together unless one EA is disabled (FB→VCC). |
| VSNSP/VSNSN (6,5) | Differential remote sense inputs | VSNSP connects to load-side VOUT; VSNSN connects to load-side SGND - removes PCB trace resistance from regulation loop. |
| ISNS1P/ISNS1N (22,21) | Phase 1 current sense inputs | Accept DCR voltage across inductor or sense resistor; support bidirectional sensing with NOC fault detection. |
| RUN1/RUN2 (24,17) | Independent channel enable | Logic-high (>2.25V) enables channel; <2V forces shutdown; internal 1.5μA pull-up simplifies sequencing. |
| TRACK/SS1/SS2 (32,9) | Soft-start/tracking control | 2.5μA current source charges external capacitor; voltage ramp controls output rise time or tracks another supply. |
| IAVG (28) | Master average current output | Capacitor-to-ground stores voltage proportional to master phase current - used by slave phases for current balancing. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent voltage-mode controllers | Enables two synchronized or independent outputs - e.g., 1.2V core + 3.3V I/O, or parallel 12-phase single-output. |
| Programmable current limit per phase | ILIM1/ILIM2 pins source 20μA - set threshold via resistor to SGND; supports adaptive OC/NOC protection. |
| Prebiased load safe startup | Bottom MOSFET disabled during soft-start; periodic 20ns pulses every 8 cycles recharge gate driver bootstrap caps. |
| PLL-synchronizable clock output | CLKOUT drives other LTC3860s without external filter; PHSMD configures phase offsets for optimal ripple cancellation. |
| Differential remote sense amplifier | 0.993–1.007 V/V gain, <2mV offset, 20MHz BW - maintains ±0.5% output accuracy across board voltage drops. |
Applications
| Telecom Base Station Power | DSP/ASIC Core Supply |
|---|---|
Use Scenario: High-current 12V-to-1.2V conversion for multi-core baseband processors in 5G macrocells. IC Role / Device Role / Timing Role: Dual-phase master controller coordinating six LTC3860s in 12-phase configuration with CLKOUT daisy-chain and IAVG current sharing. Use Value: Achieves <1% output droop under 50A transient steps while minimizing output capacitance via 1.25MHz operation and feedforward line regulation. | Use Scenario: Sequenced 0.85V/1.1V dual-rail supply for FPGA+ARM SoC with strict voltage tracking during startup. IC Role / Device Role / Timing Role: Independent channel control with TRACK/SS1 and TRACK/SS2 pins tied to shared RC network for ratiometric ramp. Use Value: Ensures <50mV inter-rail tracking error during soft-start, preventing latch-up or I/O contention in mixed-voltage systems. |
| Industrial PLC CPU Module | High-Density Server VRM |
Use Scenario: 24V input distributed power system powering multiple isolated 3.3V/5V rails in harsh factory environments. IC Role / Device Role / Timing Role: Single LTC3860IUH#PBF operating in 2-phase mode with VINSNS feedforward for immunity to 24V bus fluctuations. Use Value: Maintains ±1% output regulation during ±3V line transients (7V–14V steps), eliminating need for upstream LDO post-regulation. | Use Scenario: Scalable 48V-to-0.8V VRM for AI accelerators requiring >300A with <10mV dynamic deviation. IC Role / Device Role / Timing Role: Master LTC3860IUH#PBF controlling five slave units via CLKOUT/PHSMD, using DCR sensing for lossless current monitoring. Use Value: Enables 12-phase interleaving with <500ps phase skew, reducing input/output ripple by 70% vs. single-phase design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-phase synchronous buck controller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MP2960GQ-Z | Integrated MOSFET drivers; no external gate driver required; fixed 600kHz/1MHz options only; no IAVG pin for analog current sharing. | Best for space-constrained designs where gate drive integration reduces BOM count; unsuitable for >100A or ultra-low-noise applications requiring phase interleaving. | Select MP2960GQ-Z when gate driver integration and simplified layout outweigh need for programmable frequency or master-slave current balancing. |
| TPS546D24RQFPR | Single-channel, 60A integrated power stage; PMBus interface; digital loop compensation; no DCR sensing support; requires external current sense resistors. | Ideal for digitally managed server VRMs needing telemetry and adaptive margining; lacks dual independent channels and analog multiphase coordination. | Choose TPS546D24RQFPR for closed-loop telemetry, firmware updates, and compliance with PMBus 1.3 - not for analog polyphase scaling. |
Compared with MP2960GQ-Z and TPS546D24RQFPR, the LTC3860IUH#PBF uniquely combines dual analog controllers, DCR sensing, IAVG-based current sharing, and flexible phase synchronization - making it the only option for high-reliability, high-current analog polyphase systems requiring deterministic timing and minimal component count per phase.
Availability
LTC3860IUH#PBF is available at Aetrix Electronics and suitable for telecom base station power, industrial PLC CPU modules, and high-density server VRM designs requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LTC3860IUH#PBF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices acquired Linear Technology in 2017 and maintains full product support, documentation, and manufacturing continuity for all Linear power management ICs.
The LTC3860IUH#PBF belongs to Linear's PolyPhase® controller family, designed specifically for high-current, multi-phase DC/DC conversion in telecom infrastructure, datacenter power, and industrial computing where analog precision, thermal robustness, and phase scalability are critical.
FAQ
What is the maximum number of phases supported by the LTC3860IUH#PBF?
The LTC3860IUH#PBF supports up to 12-phase operation by daisy-chaining up to six individual LTC3860IUH#PBF controllers using CLKOUT and PHSMD pins. Each IC contributes two phases, and phase offsets are programmable in 60° increments to minimize input/output ripple and optimize thermal distribution across the PCB.
Does the LTC3860IUH#PBF support startup into a prebiased output?
Yes, the LTC3860IUH#PBF safely powers prebiased loads: during soft-start, the bottom MOSFET is disabled to prevent reverse current, while periodic 20ns pulses every 8 cycles recharge the gate driver bootstrap capacitor. This behavior is inherent to the LTC3860IUH#PBF and requires no external circuitry.
How does the LTC3860IUH#PBF achieve current sharing between phases?
The LTC3860IUH#PBF achieves current sharing via analog IAVG-based master-slave architecture: the master phase's current sense amplifier output is averaged at the IAVG pin; slave phases compare their sensed current to this reference using internal integrators, then sum the error with COMP voltage to adjust duty cycle - ensuring <5% phase current imbalance across temperature and load.
Can the LTC3860IUH#PBF operate with only one channel active?
Yes, the LTC3860IUH#PBF can operate in single-channel mode: tie FB2 to VCC to disable Channel 2's error amplifier, connect COMP2 to SGND, and use only RUN1, TRACK/SS1, and associated sense/limit pins. Channel 1 retains full functionality including DCR sensing, soft-start, and PGOOD reporting - confirmed in the LTC3860IUH#PBF datasheet Figure 10.
What is the purpose of the VINSNS pin on the LTC3860IUH#PBF?
The VINSNS pin on the LTC3860IUH#PBF provides line feedforward compensation: it injects input voltage variation directly into the PWM comparator ramp generator, enabling instantaneous duty cycle adjustment during VIN transients. This reduces output overshoot/undershoot by >60% compared to standard voltage-mode control and makes loop gain independent of input voltage - a documented feature of the LTC3860IUH#PBF.
LTC3860IUH#PBF Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- PolyPhase®
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tube
- Product Status:
- Active
- Output Type:
- PWM Signal
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Number of Outputs:
- 2
- Output Phases:
- 2
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Frequency - Switching:
- 250kHz ~ 1.25MHz
- Duty Cycle (Max):
- 91.5%
- Synchronous Rectifier:
- No
- Clock Sync:
- No
- Serial Interfaces:
- -
- Control Features:
- Current Limit, Enable, Frequency Control, Phase Control, Power Good, Soft Start, Tracking
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 32-QFN (5x5)
LTC3860IUH#PBF FAQ
1.How can I place an order for LTC3860IUH#PBF through Aetrix?
Please submit a Request for Quotation (RFQ) for LTC3860IUH#PBF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LTC3860IUH#PBF reliable?
The price and inventory of LTC3860IUH#PBF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LTC3860IUH#PBF is usually 5 days.
3.What payment methods are accepted for LTC3860IUH#PBF?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LTC3860IUH#PBF transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LTC3860IUH#PBF?
LTC3860IUH#PBF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LTC3860IUH#PBF order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LTC3860IUH#PBF?
For technical support, including LTC3860IUH#PBF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LTC3860IUH#PBF requirements.
6.How does Aetrix verify that LTC3860IUH#PBF is sourced from the original manufacturer or authorized distributors?
All LTC3860IUH#PBF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LTC3860IUH#PBF meets industry standards.
7.What is the process for return or replacement of LTC3860IUH#PBF?
All LTC3860IUH#PBF units undergo pre-shipment inspection (PSI). If there is an issue with LTC3860IUH#PBF, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LTC3860IUH#PBF part is unused and in its original packaging.
Return procedure for LTC3860IUH#PBF:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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